NAND Flash Controller Cache Buffering for Read Error Mitigation
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Solution Overview
Problem
Multi-level NAND flash memory systems experience increased read errors immediately after programming due to unstable threshold voltage distributions, which can be mitigated by introducing a delay period for reading recently programmed pages, but this approach leads to unacceptable read performance.
Innovation Solution
A controller temporarily buffers recently programmed pages in a cache and applies adjusted read voltage thresholds based on the read-after-write delay and device aging to mitigate read errors, allowing for immediate read access without waiting for the delay period to elapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay period is introduced to allow threshold voltage distributions to settle before reading, then read errors are reduced, but read performance becomes unacceptable
Solution Approach 1:
The patent applies preliminary action by pre-programming compensation values into the memory cell before the threshold voltage distribution settles. These compensation values are stored in advance and automatically applied during the read operation to counteract the unstable state, allowing immediate reading without waiting for the delay period to elapse.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on the read-after-write delay time. By adjusting the read voltage threshold according to how much time has passed since programming, the system compensates for the unstable threshold voltage distribution, enabling accurate reads even during the settling period without requiring a delay.
2Reliability
If read voltage thresholds are adjusted based on read-after-write delay and device aging, then read errors are mitigated, but device complexity increases
Solution Approach 1:
The controller pre-calculates and stores compensation values in a lookup table during manufacturing or initialization, based on expected read-after-write delay times and device aging characteristics. This preliminary preparation eliminates the need for complex real-time calculations during operation, reducing controller complexity while maintaining read accuracy.
Solution Approach 2:
The system implements feedback by monitoring the read-after-write delay time and device aging state, then automatically selecting the appropriate compensation value from the pre-stored table. This feedback mechanism enables adaptive read voltage adjustment without requiring complex real-time analysis, balancing reliability improvement with acceptable controller complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces read errors and maintains acceptable read performance by using cache buffering and adaptive read voltage thresholds, applicable to MLC, TLC, and QLC NAND flash memories.
Implementation Method 1
The amount of charge on the floating gate modulates the threshold voltage of the transistor. By applying a proper read voltage and measuring the amount of current, the programmed threshold voltage of the memory cell can be determined and thus the stored information can be detected.
Implementation Method 2
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure.
Data Source
AI summary
Read errors following programming in a multi-level non-volatile memory are mitigated by a controller of the non-volatile memory. The controller temporarily buffers, in a cache, pages of data programmed into the non-volatile memory. In response to receiving a read request for a target page of data programmed into the non-volatile memory, where the read request is received during a delay time affecting the target page, the controller services the read request by accessing data of the target page in the cache in response to the read request hitting in the cache. The controller instead services the read request from the non-volatile memory in response to the read request missing in the cache. When servicing the read request from the non-volatile memory, the controller preferably reads the target page from the non-volatile memory utilizing a set of read voltage thresholds determined based on the read-after-write delay.