NAND Flash Controller Dummy Write Synchronization

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Solution Overview

Problem

Multi-level cell (MLC) and tri-level cell (TLC) NAND flash memory technologies face performance bottlenecks due to speed mismatches between lower and upper pages during write operations, leading to inefficient use of channels and reduced write performance in solid-state drives.

Innovation Solution

A method is introduced where a NAND flash controller determines the lowest unused page number across multiple channels and performs dummy writes to synchronize page numbers, allowing for simultaneous access and full utilization of all channels during write cycles, thereby optimizing write performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level cell (MLC) and tri-level cell (TLC) NAND flash memory are used to increase storage density, then area bit density is improved, but write performance deteriorates due to speed mismatches between lower and upper pages

Engineering Contradiction:

Improvearea bit densityVSAvoidwrite performance

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing dummy writes to upper pages before actual data writes. This pre-synchronization ensures that upper and lower pages are both ready for simultaneous programming, eliminating the speed mismatch bottleneck. The controller proactively prepares the memory state in advance to enable full parallel channel utilization during subsequent write operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses dummy write operations as an intermediary mechanism to mediate between the fast lower page programming and slow upper page programming. These intermediary operations synchronize the timing of page preparations, allowing the system to bridge the speed gap between different page types and achieve coordinated parallel processing across multiple channels.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If multiple channels are used for parallel access to improve write speed, then productivity is improved, but channel utilization efficiency deteriorates due to wait times caused by speed mismatches

Engineering Contradiction:

Improvewrite speedVSAvoidwait time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The controller performs preliminary dummy writes to upper pages across all channels before initiating actual data writes. This advance preparation ensures that when parallel write operations commence, all channels can operate simultaneously without idle wait times, maximizing channel utilization efficiency and maintaining high productivity throughout the write process.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuity of useful action by eliminating idle wait periods in parallel channel operations. Through dummy write synchronization, the system maintains continuous productive activity across all channels, preventing any channel from being idle while others are working, thereby maximizing the continuous utilization of parallel processing resources.

Inventive Principle:

Principle #20Continuity of useful action

3Quantity of substance

If lower and upper pages are programmed separately to achieve multi-bit storage, then area bit density is improved, but manufacturing precision requirements increase due to need for higher programming and sensing granularity

Engineering Contradiction:

Improvearea bit densityVSAvoidprogramming and sensing granularity

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies segmentation by dividing the multi-bit storage programming into separate lower page and upper page operations. Each page is programmed independently with appropriate precision requirements, allowing the system to achieve multi-bit storage per cell while managing manufacturing precision demands through staged, granular programming sequences rather than attempting simultaneous multi-bit programming.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances write performance by synchronizing page numbers across channels, ensuring that all channels are utilized efficiently, reducing wait times and improving overall write speed in MLC and TLC NAND flash-based solid-state drives.

Implementation Method 1

NAND flash memory comprises chains of floating gate transistors that store information by injecting electrons into the floating gate via Fowler Nordheim tunneling

Methodology Applied

Scientific EffectFowler Nordheim tunneling:

Data Source

PatentUS8724389B2Non-volatile solid state memory-based mass storage device and methods thereof

Publication Date: 2014.05.13 KIOXIA CORP

AI summary

Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a NAND flash controller, an array of NAND flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the NAND flash memory integrated circuits that are simultaneously accessible at any given time by a write command. The storage device has further means for programming a dummy write to at least a first write target block in a first NAND flash memory integrated circuit within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second write target block in a second NAND flash memory integrated circuit in the group of NAND flash memory integrated circuits.