NAND Flash Controller Emulating SBC via MBC Data Aggregation

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Solution Overview

Problem

Compatibility issues between Single Bit per Cell (SBC) and Multiple Bit per Cell (MBC) NAND flash memory devices hinder the integration of MBC devices with SBC-compliant host devices, due to differences in data page and block sizes, voltage spacing, and error correction schemes, limiting the proliferation of MBC technology despite its cost-effectiveness and higher storage capacity.

Innovation Solution

A controller is developed to manage interactions between SBC and MBC devices by aggregating host data with complementary data, parsing data during write and read operations, and handling erase instructions, enabling SBC data to be written and read as regular MBC data, and ensuring compatibility through a pseudo Partial Page Programming scheme.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If MBC NAND flash memory devices are used to increase storage capacity and cost-effectiveness, then storage density and cost-performance are improved, but compatibility with SBC-compliant host devices deteriorates due to differences in data page and block sizes, voltage spacing, and error correction schemes

Engineering Contradiction:
Improvestorage capacityVSAvoidcompatibility with SBC hosts
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent introduces a compatibility layer or translation mechanism that acts as an intermediary between SBC host devices and MBC flash memory devices. This intermediary handles the conversion and adaptation of data page sizes, block sizes, voltage spacing, and error correction schemes, allowing SBC hosts to communicate with and utilize MBC devices without direct compatibility. The controller translates SBC-compatible commands into MBC-specific operations, enabling seamless integration while maintaining the benefits of MBC technology.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If data page sizes and block sizes are standardized for SBC devices, then ease of operation and compatibility are improved, but the ability to utilize higher-density MBC configurations deteriorates

Engineering Contradiction:
ImprovecompatibilityVSAvoidMBC configuration flexibility
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic sizing and configuration capabilities where the controller can adaptively adjust data page sizes and block sizes based on the specific MBC device being used and the requirements of the SBC host. This dynamic approach allows the system to maintain SBC compatibility interfaces while internally optimizing for MBC configurations, enabling flexible adaptation to different device densities and host requirements without being constrained by fixed SBC standards.

Inventive Principle:
Principle #15Dynamics

3Reliability

If voltage spacing is optimized for SBC reliability, then error correction and data integrity are improved, but storage density achievable with MBC cells deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidstorage density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent employs parameter changes and adaptive voltage threshold adjustment mechanisms that allow the system to optimize voltage spacing dynamically based on whether reliability or density is the priority. The controller can adjust read voltage thresholds, programming voltages, and verification criteria to match the specific requirements of the application. This enables the system to achieve high reliability when needed while maximizing storage density when capacity is the primary concern, effectively decoupling the trade-off between these two parameters.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8683116B2Controller for one type of NAND flash memory for emulating another type of NAND flash memory
Publication Date: 2014.03.25 WESTERN DIGITAL ISRAEL LTD
  • US8683116B2 patent drawing
  • US8683116B2 patent drawing
  • US8683116B2 patent drawing

AI summary

A method of executing reading instruction to read host data from a flash memory device is provided. The method initiates with receiving from a host device a read instruction to read host data from an array of NAND flash memory cells grouped into separately-readable device pages, the host data being a portion of device data that is stored in a device page. The host data is parsed from device data, and the parsed host data is sent to the host device.