NAND Flash Controller Power Interruption Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

NAND flash memory devices used in telematics applications experience data corruption due to charge gain during power interruptions, leading to unreliable operation and failure of critical functions like eCall, which requires high reliability.

Innovation Solution

A control apparatus for NAND flash memory devices that includes a controller and an auxiliary power circuit to block commands during power instability, supply auxiliary power to complete ongoing operations, and perform controlled power-off and power-on sequences to prevent data corruption and ensure reliable operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power supply interruption occurs during NAND flash memory operations, then data corruption due to charge gain occurs, but the memory device cannot complete ongoing program or erase operations

Engineering Contradiction:
Improvedata integrityVSAvoidoperation completion time
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The controller detects power supply interruption in advance during ongoing program or erase operations and activates the auxiliary power circuit immediately to maintain power supply, allowing the operation to complete without data corruption. This preliminary detection and response mechanism prevents the harmful effect before it can occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The auxiliary power circuit serves as a cushioning mechanism that activates when main power is interrupted, providing backup power to complete ongoing memory operations. This beforehand prepared backup power source prevents data corruption by maintaining stable power supply during critical operation periods.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If the controller blocks command signals during power instability, then data corruption is prevented, but memory access is delayed

Engineering Contradiction:
Improvedata integrityVSAvoidmemory access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller dynamically adjusts its behavior based on power supply stability detection. During unstable power conditions, it blocks command signals to prevent data corruption. When power stabilizes, it resumes normal operations. This dynamic adaptation optimizes the balance between data integrity and access speed.

Inventive Principle:
Principle #15Dynamics

3Reliability

If auxiliary power is supplied to complete ongoing operations during power interruption, then data corruption is prevented, but power consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The auxiliary power circuit is activated only when power supply interruption is detected during ongoing program or erase operations. By applying counter-action (backup power) only when needed, the system prevents data corruption without unnecessarily increasing power consumption during normal operation.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The system changes the power supply parameter dynamically - switching from main power to auxiliary power only when interruption is detected. This parameter change ensures data integrity during critical operations while minimizing overall power consumption by activating the auxiliary circuit only when necessary.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240290397A1Apparatus for controlling NAND flash memory device and method for controlling same
Publication Date: 2024.08.29 LG INNOTEK CO LTD
  • US20240290397A1 patent drawing
  • US20240290397A1 patent drawing
  • US20240290397A1 patent drawing

AI summary

A control apparatus for a NAND flash memory device including a NAND flash memory, a controller configured to generate a command signal to program, read, and erase data in the NAND flash memory, and an auxiliary power circuit configured to maintain power for operating the memory and the controller during a first time from a first time point when a voltage of a supply power is less than a preset voltage, wherein the controller is configured to block the command signal during the first time, and wherein power supplied to the memory is blocked regardless of a level of a voltage of the supply power for at least a second time from a second time point after the first time.