NAND Flash Memory Controller Read Verify Bad Blocking
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Solution Overview
Problem
Current memory systems using NAND flash memory face challenges in ensuring data reliability due to burst failures during write and read operations, where error correction capabilities are consumed by physical failures, leaving less capacity for correcting accidental failures over time.
Innovation Solution
The memory system incorporates a memory controller that performs a read verify operation immediately after writing data, allowing for the detection of physical failures and reducing accidental failures by shifting the read voltage to minimize failed bits, and implements a bad blocking process to invalidate faulty memory regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction capabilities are used to handle physical failures during write and read operations, then data reliability is improved, but the error correction capacity is consumed, leaving less capability for correcting accidental failures over time
Solution Approach 1:
The patent performs a read verify operation immediately after a write operation to detect physical failures before they accumulate. This preliminary detection allows the system to identify and mark faulty memory regions (bad blocking) before normal read operations are affected, preserving error correction capacity for actual data reads.
Solution Approach 2:
The patent segments the memory operation process into distinct phases: write operation, immediate read verify operation, and normal read operations. By separating the verification function from normal operations, the system can handle physical failures independently without consuming error correction resources during regular data access.
2Reliability
If read verify operation is performed immediately after write operation, then physical failures are detected early and error correction capacity is preserved, but operation time increases
Solution Approach 1:
The read verify operation is performed immediately after the write operation without interruption, creating a continuous verification process. This eliminates idle time between write and verify operations, ensuring that the memory region is validated while still in the write-complete state, thereby minimizing total operation time while maintaining high reliability.
3Measurement precision
If read voltage is shifted to minimize failed bits, then data accuracy is improved, but voltage control complexity increases
Solution Approach 1:
The system uses feedback from the read verify operation to determine whether voltage shifting is needed. By monitoring the results of read operations and comparing them against expected values, the controller can dynamically adjust the read voltage to optimize data accuracy while only applying complexity when actually needed based on detected conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data reliability by accurately identifying and addressing physical failures during read operations, reducing data defects and maintaining error correction capabilities for accidental failures, thus improving overall system performance.
Implementation Method 1
reducing accidental failures by shifting the read voltage to minimize failed bits
Data Source
AI summary
According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.