NAND Flash Controller Threshold Voltage Correction for Retention
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Solution Overview
Problem
The increasing demand for non-volatile memory devices with higher integration density, as driven by Industry 4.0, has led to challenges in maintaining retention performance and data integrity due to lateral charge migration and deep-erased cells in NAND flash memory devices.
Innovation Solution
A semiconductor device and its operating method that include a memory device and a controller capable of performing an erase operation, a correction operation on the threshold voltage of deep-erased cells, and an erase verify operation to ensure threshold voltages fall within a predefined range, thereby enhancing retention performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile memory devices are scaled down to increase integration density, then the density of integration is improved, but retention performance deteriorates due to lateral charge migration and deep-erased cells
Solution Approach 1:
The controller performs a correction operation on deep-erased cells before the program operation to adjust their threshold voltages. This preliminary action prevents retention issues from developing, allowing the memory device to maintain high integration density while preserving retention performance through proactive threshold voltage correction.
Solution Approach 2:
The controller performs erase verify operations to identify deep-erased cells and implements a feedback mechanism where cells failing the verify operation undergo correction operations. This closed-loop control ensures that threshold voltages are adjusted back to acceptable ranges, maintaining retention performance despite high integration density scaling.
2Quantity of substance
If erase operation is performed on memory blocks, then data storage capacity is improved, but deep-erased cells are generated causing retention degradation
Solution Approach 1:
The controller converts the harmful effect of deep-erased cells (caused by erase operations) into a manageable condition by detecting cells with threshold voltages below the verify level and applying correction operations. This transforms the harmful deep-erased state into a corrected state, allowing continuous erase operations while maintaining retention performance.
Solution Approach 2:
The controller changes the threshold voltage parameter of deep-erased cells from below the verify level to above the verify level through correction operations. This parameter adjustment restores proper retention characteristics to cells that were degraded by erase operations, enabling repeated erase cycles without permanent retention degradation.
3Reliability
If correction operation is performed on deep-erased cells, then retention performance is improved, but operation complexity increases
Solution Approach 1:
The controller applies correction operations selectively only to deep-erased cells that fail the erase verify operation, rather than processing all cells uniformly. This localized approach improves retention performance where needed while minimizing unnecessary operations, thereby reducing overall operational complexity compared to blanket correction of all cells.
Data Source
AI summary
A semiconductor device includes a memory device and a controller configured to perform an erase operation on the memory device, perform a correction operation for a threshold voltage of a deep-erased cell, and perform an erase verify operation by identifying whether threshold voltages of a plurality of cells of the memory device fall within a predefined range.