NAND Flash In-Memory Convolution Using Page Buffer Current Sensing
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Solution Overview
Problem
Neural network operations in existing technologies require specific memory array structures and numerous peripheral circuits, leading to high costs and unsuitability for mass production when using NOR memory architecture or ReRAM/PCM memory architecture.
Innovation Solution
A method for controlling a NAND flash memory to perform neural network operations by writing weight data into memory cells, applying a target voltage, and sensing current using page buffers to obtain convolution results, leveraging the existing structure of NAND flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NOR memory architecture or ReRAM/PCM memory architecture is used for neural network operation, then neural network operation capability is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes generic NAND flash memory perform neural network operations by utilizing its existing structure for both traditional storage and in-memory computing functions. The same memory cells, bit lines, and word lines are used for both data storage and convolution operations, eliminating the need for separate specialized hardware structures.
Solution Approach 2:
The NAND flash memory structure serves itself by using its inherent electrical characteristics (current flow through memory cells) to perform neural network computations. The memory device's natural electrical behavior is exploited to execute convolution operations without requiring additional dedicated computational circuits.
2Adaptability or versatility
If NOR memory architecture or ReRAM/PCM memory architecture is used for neural network operation, then neural network operation capability is achieved, but manufacturing cost increases
Solution Approach 1:
The patent enables existing NAND flash memory devices to perform dual functions as both storage and computing units. This eliminates the need for separate specialized neural network processing hardware, allowing mass production using established NAND flash manufacturing processes without requiring new fabrication techniques or additional cost-intensive production lines.
3Productivity
If specialized memory structures are used for neural network operation, then computing performance is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent exploits the inherent electrical characteristics of standard NAND flash memory cells to perform computing operations. The memory cells naturally conduct current based on their programmed states, and this current flow is directly measured to obtain convolution results, turning the memory device's basic electrical behavior into a computational resource without requiring specialized circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables neural network operations using generic NAND flash memory, reducing costs and making it suitable for mass production without the need for specialized arrays and peripheral circuits.
Implementation Method 1
writing weight data into the memory cell according to a relationship between the weight data and the feature data
Implementation Method 2
applying a target voltage to the memory cell by the word line
Implementation Method 3
sensing, by the page buffer, a current of the memory block, to obtain a convolution result
Data Source
AI summary
The present invention provides a method for controlling a NAND flash memory to complete neural network operation, including the following steps: providing a NAND flash memory, where the NAND flash memory includes multiple memory blocks and multiple page buffers, the memory block includes multiple synaptic strings, multiple bit lines, and multiple word lines, the synaptic string includes multiple memory cells connected in series, the synaptic strings are connected to the bit lines in one-to-one correspondence, the word line is connected to all the synaptic strings, the page buffer is connected to all the memory blocks, and one of the bit lines is merely connected to one of the page buffers; writing weight data into the memory cell according to a relationship between the weight data and the feature data; applying a target voltage to the memory cell by the word line; and sensing, by the page buffer, a current of the memory block, to obtain a convolution result. Thus, the neural network operation is achieved using a generic NAND flash memory.