NAND Flash Memory Copy Back Data Transfer Mechanism
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Solution Overview
Problem
NAND flash memory devices require significant time for programming due to the need for an erase operation before writing, and conventional data transfer methods between different planes are inefficient, limiting data transfer speed.
Innovation Solution
A non-volatile memory device with an input/output control unit that enables direct data transfer between planes using a copy back function without involving the host, utilizing the full 32-bit bandwidth within the memory area, thereby reducing programming time and data storage time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred between planes through the host, then data transfer can be completed, but programming time and data storage time are significantly increased
Solution Approach 1:
The patent introduces an internal data transfer path as an intermediary mechanism between planes, allowing data to be transferred directly through the memory device without involving the host. This internal path acts as a mediator that resolves the time-consuming host involvement while ensuring complete and reliable data transfer between planes.
Solution Approach 2:
The patent segments the data transfer function into two distinct paths: an internal direct transfer path for fast operations and an external host-mediated path for complex operations. By dividing the transfer mechanism, the system can choose the appropriate path based on requirements, thereby reducing programming time for routine operations while maintaining reliability.
2Device complexity
If conventional data transfer methods are used between planes, then system simplicity is maintained, but data transfer speed is limited
Solution Approach 1:
The patent adds a new dimension to data transfer by creating a direct internal pathway between planes that bypasses the traditional host-mediated route. This dimensional change in the transfer architecture enables faster data movement while maintaining the overall system structure, effectively increasing data transfer speed without substantially complicating the system.
3Reliability
If erase operation is performed before write operation in NAND flash memory, then data integrity is ensured, but programming time is extended to several milliseconds
Solution Approach 1:
The patent performs preliminary actions by preparing data in buffer memory before the actual write operation to the plane. This preliminary data preparation and staging allows the erase and write operations to proceed more efficiently, reducing the overall programming time while ensuring data integrity through proper sequencing of operations.
Solution Approach 2:
The patent maintains continuity of useful action by enabling parallel operations: while one plane is being erased, data can be prepared in buffers, and other planes can be accessed. This continuous utilization of memory resources eliminates idle time and reduces the overall programming time while maintaining data integrity through proper operation sequencing.
Data Source
AI summary
A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.