NAND Flash Memory Structure for Lower Cell-to-Cell Capacitive Coupling
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Solution Overview
Problem
Conventional NAND flash memories with a two-dimensional structure face issues of increased capacitive coupling between adjacent memory cells due to miniaturization, leading to widened threshold distribution and reduced reliability.
Innovation Solution
A NAND flash memory design that incorporates a charge storage layer with a nitride layer sandwiched between insulating layers, along with a two-layer control gate structure, where the trench isolation region is self-aligned with the charge storage and first conductive layers, reducing capacitive coupling and narrowing the threshold distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the floating gate structure is used for miniaturization, then the storage capacity is improved, but the capacitive coupling between adjacent memory cells increases
Solution Approach 1:
The patent extracts the charge storage function from the floating gate structure and implements it through a dedicated charge storage layer with nitride layer sandwiched between insulating layers. This separation allows the control gate to be positioned further from adjacent cells, reducing capacitive coupling while maintaining storage capacity.
Solution Approach 2:
The patent introduces an intermediary insulating layer structure between the charge storage layer and the control gate, as well as between adjacent memory cells. This intermediary layer acts as a barrier to reduce parasitic capacitance coupling while maintaining the necessary electrical functionality.
2Productivity
If the floating gate structure is miniaturized, then the integration density is improved, but the threshold distribution of memory cells widens
Solution Approach 1:
The patent applies local quality by creating a dedicated charge storage layer with specific nitride layer characteristics at each memory cell location, rather than using a uniform floating gate structure. This localized approach allows precise control of charge storage properties, narrowing the threshold distribution while maintaining high integration density.
3Productivity
If the control gate is positioned closer to the charge storage layer, then the programming efficiency is improved, but the coupling effect with adjacent cells increases
Solution Approach 1:
The patent resolves the contradiction by transitioning from a two-dimensional planar arrangement to a three-dimensional stacked structure. The charge storage layer is positioned between the control gate and the substrate, allowing the control gate to be optimally positioned for programming efficiency while the vertical stacking provides natural isolation from adjacent cells in the horizontal direction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively reduces capacitive coupling between adjacent memory cells, thereby improving the reliability and integration of the NAND flash memory by narrowing the threshold distribution.
Implementation Method 1
a charge storage layer, formed in the active region corresponding to each memory cell and including a nitride layer sandwiched between insulating layers
Implementation Method 2
a charge storage layer, formed in the active region corresponding to each memory cell and including a nitride layer sandwiched between insulating layers
Data Source
AI summary
A NAND flash memory capable of reducing capacitive coupling between adjacent memory cells and a manufacturing method thereof are provided. The NAND flash memory includes an active region, formed by extending along a bit line direction within a silicon substrate; a trench isolation region, used to define the active region; and a charge storage layer, formed on the active region corresponding to each memory cell and stacked with a SiN layer sandwiched between insulating layers; a first control gate, formed on the charge storage layer corresponding to each memory cell; and a second control gate, extending along a word line direction and formed on the first control gate. The second control gate is electrically connected to multiple first control gates in a corresponding row direction, and the trench isolation region is aligned with sidewalls of the first control gate and the charge storage layer.