NAND Flash Memory CSL Noise Correction via Pre-Charge Voltage
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Solution Overview
Problem
In NAND flash memory devices, common source line noise (CSL noise) affects the accuracy of read operations by unintentionally increasing the threshold voltage of memory cells, leading to misjudgment of programmed states and reduced accuracy in data read/write operations.
Innovation Solution
A semiconductor memory device with a fail bit counter and voltage controller that adjusts the read voltage and pre-charge voltage based on the number of fail cells and inhibit cells during program verification operations, correcting for CSL noise without the need for a dummy read period, thereby improving data read/write accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dummy read period is used to suppress CSL noise, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the common source line CSL to a specific voltage level before performing the verify read operation. This preliminary voltage application suppresses the CSL noise that would otherwise occur during the operation, eliminating the need for a dummy read period while maintaining read accuracy. The pre-charge voltage is set to a level that prevents threshold voltage shifts in memory cells during the verify read, thereby resolving the contradiction between measurement precision and time loss.
2Measurement precision
If read voltage is applied to verify programmed state, then measurement precision is improved, but object-generated harmful factors increase
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging the common source line to counteract the harmful effect of threshold voltage shift before it occurs. The pre-charge voltage is specifically set to compensate for the voltage drop that would occur when read voltage is applied, thereby preventing the threshold voltage shift that would otherwise lead to misjudgment of programmed states. This allows accurate detection while eliminating the harmful side effect.
3Measurement precision
If current flows through memory cells during verify read, then measurement precision is improved, but object-generated harmful factors increase
Solution Approach 1:
The patent applies preliminary action by pre-charging the common source line to a voltage level that accounts for the expected voltage increase due to current flow. By setting the pre-charge voltage appropriately before the verify read operation, the system compensates for the voltage drop caused by current flowing through memory cells, thereby maintaining measurement precision while allowing necessary current flow for data reading.
Data Source
AI summary
A semiconductor memory device operate during a program verification operation to apply a read voltage to a word line and a pre-charge voltage to a bit line in order to provide output data. A number of fail cells is determined in view of the output data, wherein the number of fail cells is directly related to an increase in voltage on a common source line (CSL) connected to memory cells providing the output data. During a subsequent program verification operation, the level of at least one of the read voltage and the pre-charge voltage is adjusted in response to the number of fail cells.