NAND Flash Data Page Management for Voltage Disturbance Mitigation

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Solution Overview

Problem

NAND flash memory devices experience frequent errors in data pages closest to the source select line (SSL) and drain select line (DSL due to voltage disturbances and stress, leading to reduced data retention and programming efficiency.

Innovation Solution

Differentiate the data pages near the SSL and DSL by using techniques such as downgrading NAND memory cell usage, employing different error correcting codes, data compression, weighted wear leveling, and varying data page utilization scheduling, and configuring multi-level NAND memory cells as single-level cells for specific pages after a predetermined number of cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is stored in data pages closest to SSL and DSL, then storage capacity is utilized, but error frequency increases due to voltage disturbances and stress

Engineering Contradiction:
Improveerror frequencyVSAvoidvoltage disturbances and stress
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by differentiating management strategies for different data page regions. Data pages closest to SSL and DSL (first and second sets) are managed differently from remaining data pages (third set). Specifically, the first and second sets use SLC mode with stronger ECC protection, while the third set uses MLC mode, optimizing reliability for pages exposed to harmful voltage disturbances and stress near the select lines

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes operational parameters based on location. Multi-level NAND memory cells are configured as single-level cells for data pages in the first and second sets (near SSL and DSL) after a predetermined number of programming and erase cycles, while remaining pages continue using multi-level configuration. This parameter change adapts the memory cells to withstand the harsher electrical conditions near the select lines

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multi-level NAND memory cells are used for all data pages, then storage density is maximized, but data retention deteriorates in pages near SSL and DSL

Engineering Contradiction:
Improvedata retentionVSAvoidmemory cell configuration management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the plurality of data pages into three distinct sets: a first set closest to SSL, a second set closest to DSL, and a third set of remaining pages. This segmentation allows differentiated configuration management where the first and second sets use SLC mode with enhanced protection, while the third set uses MLC mode, balancing data retention with manageable complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic configuration of memory cells based on operational cycles and location. Multi-level NAND memory cells are dynamically switched between SLC and MLC modes depending on the number of programming and erase cycles performed and their proximity to SSL/DSL. This dynamic adaptation optimizes data retention while managing the complexity of configuration through automated cycle-based transitions

Inventive Principle:
Principle #15Dynamics

3Reliability

If uniform wear leveling is applied across all data pages, then simplicity is maintained, but wear distribution becomes uneven due to differential stress near SSL and DSL

Engineering Contradiction:
Improvewear distributionVSAvoidwear leveling algorithm
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality to wear leveling by implementing weighted wear leveling that accounts for location-specific stress. Data pages in the first and second sets (near SSL and DSL) are assigned different wear weights compared to the third set, reflecting the differential stress and error susceptibility. This localized approach ensures more accurate wear distribution while managing algorithmic complexity through position-based weighting factors

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8223545B1Systems and methods for data page management of NAND flash memory arrangements
Publication Date: 2012.07.17 SAMSUNG ELECTRONICS CO LTD
  • US8223545B1 patent drawing
  • US8223545B1 patent drawing
  • US8223545B1 patent drawing

AI summary

Embodiments of the present disclosure provide methods and apparatus for providing a NAND flash memory arrangement that comprises a source select line (SSL), a drain select line (DSL) and a plurality of NAND memory cells arranged to provide a plurality of data pages. The method further includes defining a first set of data pages in close proximity to the SSL, defining a second set of data pages in close proximity to the DSL, and differentiating the first set of data pages and the second set of data pages from at least the remaining data pages.