NAND Flash Data Path Integrity Verification
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Solution Overview
Problem
Current memory devices face challenges in distinguishing between data path bit errors and array bit errors, which are difficult to correct and can lead to unpredictable and sporadic errors, affecting data integrity in NAND flash memory devices.
Innovation Solution
The method involves verifying data path integrity by loading and comparing sets of data within the cache and page registers during programming and read operations, using a debug mode to bypass array bit errors and confirm data path integrity by matching data sets, thereby differentiating between data path and array bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction schemes (LDPC) are used to correct bit errors, then data integrity is improved, but hard errors (data path bit errors) become more difficult to correct and consume much more error correction resources
Solution Approach 1:
The patent segments error detection into two distinct paths: array path errors (detected via ECC) and data path errors (detected via data path verification). By dividing the error detection mechanism, the system can identify and handle hard errors separately, preventing them from consuming excessive ECC resources and allowing more efficient error correction for array path errors.
Solution Approach 2:
The patent introduces an intermediary verification mechanism (data path verification) between the data path and the ECC system. This intermediary layer detects data path errors before they reach the ECC corrector, acting as a filter that prevents hard errors from overwhelming the error correction resources.
2Ease of manufacture
If memory density is increased using multilevel cells (MLC) to reduce system costs, then manufacturing cost is reduced, but data path errors can further corrupt or increase the rate or severity of array path errors
Solution Approach 1:
The patent performs preliminary verification of data path integrity during programming operations by comparing test data before array programming completes. This preliminary action detects data path errors early, preventing them from corrupting array path errors and compromising data integrity, while maintaining the cost benefits of MLC technology.
Solution Approach 2:
The patent implements a feedback mechanism where data path verification results are used to identify and flag data path errors. This feedback allows the system to distinguish between data path and array path errors, enabling targeted error handling that preserves data integrity without sacrificing the manufacturing advantages of MLC.
3Reliability
If data path verification is performed during array operations by reading and comparing data sets, then data path integrity can be verified in real-time, but additional verification steps increase operation time
Solution Approach 1:
The patent merges data path verification with existing array operations by performing verification during programming and read operations. Instead of adding separate verification steps, the verification is combined with normal operations, minimizing additional time overhead while achieving real-time data path integrity verification.
Solution Approach 2:
The patent performs partial verification by focusing on critical data paths and using comparison of data sets written to and read from registers. This partial verification approach provides sufficient data path integrity checking without requiring exhaustive verification of all possible error conditions, thus limiting time loss while maintaining reliability.
Data Source
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AI summary
Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device. The read first set of data and the data written to the first register are compared to verify data path integrity.