NAND Flash String Writes Using Divisional 1-2-4-8 Coding

The patent divides a single write operation into multiple sequential write operations (first write operation and second write operation). The first write operation writes data to memory cells while the second write operation writes remaining data after a predetermined time has elapsed. This segmentation allows the system to mitigate initial drop and parasitic capacitance effects by spacing out the write operations, thereby improving data reliability while maintaining acceptable write speed through efficient parallel processing of multiple strings.

The patent implements an internal data load (IDL) function that enables the controller to automatically restore and correct data using its existing resources. The IDL function utilizes the controller's internal buffer memory to store and restore data patterns, allowing the system to perform self-correction of data errors without requiring additional external RAM. This self-service mechanism improves data restoration capability while avoiding increased device complexity and cost.

The patent combines multiple write operations by dividing data into multiple strings that can be written in parallel. The controller divides the data to be written across multiple strings, allowing simultaneous write operations to different memory blocks. This merging approach maintains data accuracy through controlled sequential writes while reducing total write time through parallel processing capability, effectively resolving the time-accuracy tradeoff.