NAND Flash Divisional Write Scheme for Threshold Voltage Reliability
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Solution Overview
Problem
NAND flash memory systems face challenges in maintaining data reliability due to initial drop and parasitic capacitance effects during write operations, leading to deviations in threshold voltage distributions and reduced data integrity.
Innovation Solution
The implementation of a 1-2-4-8 code data assignment and divisional write operations, where 4-page data is written in two separate write operations, with the first write operation focusing on lower and middle bits and the second on upper bits, while also employing internal data load (IDL) to manage threshold voltage variations and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written to NAND flash memory in a single write operation, then write speed is improved, but threshold voltage distribution spread increases and data reliability deteriorates
Solution Approach 1:
The write operation is divided into multiple separate write operations, where each operation writes a portion of the data (e.g., lower bits in first operation, upper bits in second operation). This segmentation reduces the spread of threshold voltage distributions during each write operation, thereby improving data reliability while maintaining acceptable overall write speed through optimized data assignment patterns.
2Reliability
If data is written in multiple separate write operations, then threshold voltage distribution spread is reduced and data reliability is improved, but write speed deteriorates
Solution Approach 1:
Data is pre-processed and assigned to specific write operations using a 1-2-4-8 code pattern before writing. This preliminary organization of data ensures that each write operation targets specific bit patterns that minimize threshold voltage spread, allowing the system to achieve both high reliability and optimized write performance without requiring multiple sequential writes for the same data portion.
3Device complexity
If conventional data assignment is used during write operations, then device complexity is low, but parasitic capacitance effects increase and data integrity deteriorates
Solution Approach 1:
The data assignment pattern is changed from conventional sequential writing to a 1-2-4-8 code-based pattern that assigns specific bit weights to different write operations. This parameter change in data organization minimizes parasitic capacitance effects by ensuring that write operations target memory cells in a pattern that reduces electrical interference, thereby improving data integrity without significantly increasing device complexity.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.