Hardware Accelerated DSP Error Recovery for NAND Flash
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Solution Overview
Problem
NAND flash devices experience data retention issues due to charge leakage from floating gates, accelerated by high temperature and program-erase cycles, leading to cell voltage driftage that can cause detection errors beyond the correction capabilities of error-correcting code decoders.
Innovation Solution
Implementing a hardware-based system with a cell voltage driftage indicator monitor and error recovery controller to detect and correct cell voltage driftage by adjusting read threshold values, allowing for earlier and more reliable error recovery before ECC decoder failure, thereby reducing the need for extensive iterations and optimizing processing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed using traditional ECC decoder methods, then data integrity can be maintained, but the system experiences delayed error detection and excessive processing iterations when cell voltage driftage occurs
Solution Approach 1:
The patent implements a driftage indicator monitor that continuously monitors cell voltage levels and detects driftage conditions before they cause detectable read errors. This preliminary detection allows the system to initiate error recovery procedures earlier, preventing the need for extensive iterative processing that would occur if waiting for ECC decoder failure. The monitor compares reference voltages against threshold values and triggers recovery when driftage is detected, rather than waiting for actual data corruption.
Solution Approach 2:
The patent replaces the traditional mechanical/software-based iterative ECC decoding process with a hardware-accelerated error recovery mechanism. The driftage indicator monitor and error recovery controller are implemented as hardware components that can rapidly detect and correct errors through direct voltage level adjustments, bypassing the time-consuming iterative software decoding process. This hardware substitution enables faster response to cell voltage driftage while maintaining data integrity.
2Reliability
If extensive iterative processing is performed by the ECC decoder to correct errors, then data recovery may be achieved, but processing resources are excessively consumed
Solution Approach 1:
By implementing continuous monitoring of cell voltage driftage through the driftage indicator monitor, the system detects errors before they require complex ECC decoding iterations. This preliminary detection allows the error recovery controller to apply corrective voltage adjustments proactively, preventing the need for resource-intensive iterative processing. The system performs maintenance-like corrections based on driftage detection rather than reactive recovery requiring extensive computation.
Solution Approach 2:
The hardware-based error recovery system enables the flash memory device to self-correct errors autonomously without requiring extensive external processing resources. The error recovery controller directly adjusts read threshold voltages based on driftage indicator signals, allowing the memory device to service its own errors through hardware-level voltage compensation rather than relying on software-based iterative decoding that consumes significant processing energy.
3Measurement precision
If read threshold values are adjusted frequently to compensate for cell voltage driftage, then detection accuracy improves, but system complexity increases
Solution Approach 1:
The patent introduces a driftage indicator monitor as an intermediary component that simplifies the complexity of managing read threshold adjustments. Instead of requiring complex algorithms to determine when and how to adjust thresholds, the monitor provides direct hardware signals indicating driftage conditions. This intermediary translates complex voltage driftage patterns into simple binary indicators that trigger predetermined recovery actions, reducing the overall system complexity while maintaining high measurement precision through hardware-level voltage monitoring.
Data Source
AI summary
A method for correcting a cell voltage driftage in a NAND flash device is disclosed. An indicator indicating a cell voltage driftage in a memory unit of a NAND flash device is monitored by a processor. A cell voltage driftage in the NAND flash device is detected based at least in part on the indicator. One or more NAND commands correcting the cell voltage driftage are generated. The one or more NAND commands include a NAND command associated with changing a configuration setting of the NAND flash device.