NAND Flash Memory Dual-Buffer Simultaneous Write Architecture
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Solution Overview
Problem
Current NAND flash memory systems face challenges in writing data securely and efficiently at high speeds, as they require writing identical data to multiple areas to ensure backup, which increases write time and reduces system throughput.
Innovation Solution
A memory system with first and second districts, where a control section simultaneously writes the same data to both districts using a defined command sequence, eliminating the need to write data twice and improving throughput by allowing simultaneous writing with a single command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identical data is written to multiple areas to prepare backup, then data security is improved, but write time increases and system throughput is reduced
Solution Approach 1:
The patent merges the backup writing operation with the original data writing operation into a single simultaneous process. By using a dual buffer architecture where data is written to both the main buffer and backup buffer concurrently through a single write command, the system achieves data security without requiring sequential writing operations, thus maintaining high throughput
2Reliability
If identical data is written to multiple areas to prepare backup, then data security is improved, but write time increases
Solution Approach 1:
The patent implements continuous useful action by performing both original data writing and backup writing simultaneously in parallel without interruption. The dual buffer architecture enables both writing operations to proceed concurrently, eliminating the sequential time loss that would occur if backup writing had to wait for the original writing to complete
3Reliability
If data is written to a different area for backup, then data security is improved, but device complexity increases due to multiple writing operations
Solution Approach 1:
The patent applies universality by designing a single write command interface that performs multiple functions simultaneously - both original data writing and backup writing are accomplished through one unified command. The dual buffer system is controlled by a single controller that manages both writing operations, reducing the complexity that would arise from requiring separate control mechanisms for each writing operation
Data Source
AI summary
A memory system includes first and second districts, and a control section. Each of the first and second districts includes a memory cell array. The control section receives a single write command to simultaneously write first data to the first and second districts. A memory controller may subsequently issue a read command to read the first data from one of the memory cell arrays to determine whether the read first data is normal or is correctable based on a result of error correction in an error correction circuit. When the read first data is normal or is correctable, the first data written to the other of the memory cell arrays may be deleted or nullified.