NAND Flash Memory Cell Array With Dual Control Gates
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Solution Overview
Problem
NAND type flash memories face challenges in reducing bit cost while maintaining cell capacity due to increased proximity effects and manufacturing complexity as device size decreases, making it difficult to ensure retention margins and control write operations effectively.
Innovation Solution
The nonvolatile semiconductor memory device employs a memory cell array structure with control gates embedded on both sides of floating gates, allowing for simultaneous driving of vertically corresponding memory cells and independent selection of select gate transistors for bit lines, which reduces proximity effects and improves controllability through adjusted write conditions and pulse allocation methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of NAND type flash memory decreases to increase integration, then the number of memory cells per unit area increases, but the proximity effect between adjacent memory cells intensifies and retention margins deteriorate
Solution Approach 1:
The patent divides the memory cell structure into two independent stacked layers, with each layer having its own charge accumulation layer and control gate. This segmentation allows independent control of each layer, reducing the proximity effect between adjacent memory cells while maintaining high integration density.
Solution Approach 2:
The patent transitions from a single-layer planar structure to a three-dimensional stacked structure with two layers vertically arranged. This dimensional change increases the number of memory cells per unit area while maintaining adequate spacing between cells in each layer, thereby reducing proximity effects and preserving retention margins.
2Quantity of substance
If memory cells are simply stacked to increase cell capacity, then the storage capacity increases, but the number of manufacturing steps increases and bit cost rises
Solution Approach 1:
The patent merges the formation processes of two stacked memory cell layers into a unified manufacturing sequence. By forming both layers in an integrated process flow with shared steps for insulating films and electrode structures, the number of discrete manufacturing steps is reduced compared to forming layers separately, thereby controlling bit cost while achieving increased cell capacity.
3Quantity of substance
If memory cells are simply stacked to increase cell capacity, then the storage capacity increases, but bit cost increases due to reduced shrink ratio
Solution Approach 1:
The patent changes the structural parameters by implementing a two-layer stacked configuration with specific thickness ratios and material compositions. This allows optimization of the shrink ratio, achieving a balance where cell capacity increases while the reduction in bit cost per cell remains economically viable, unlike simple stacking which follows a linear 1/n shrink ratio.
4Measurement precision
If control gates are added on both sides of floating gates to reduce proximity effects, then write operation accuracy improves, but device structure becomes more complex
Solution Approach 1:
The control gates in the patent serve multiple functions simultaneously: they control the charge accumulation in their respective layer, provide electrostatic isolation to reduce proximity effects on adjacent cells, and enable independent selection and writing of specific memory cells. This multi-functionality reduces write operation errors without requiring excessively complex additional structures.
Data Source
AI summary
A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.