NAND Flash Memory Continuous Read Synchronization via Dual Latch Segmentation
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Solution Overview
Problem
NAND flash memory's continuous read function is limited by the asynchronous relationship between internal and external clock signals, restricting the frequency of the external clock signal and leading to data destruction at slow frequencies.
Innovation Solution
A semiconductor apparatus and method that adjusts the read time settings to synchronize data output with an external clock signal, allowing for high-speed continuous read by optimizing the timing of data reading and error correction processes, using multiple latches for independent data transmission and ECC processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is read from the memory cell array and held in latches during continuous read operations, then data can be output synchronously with an external clock signal, but the asynchronous relationship between internal and external clock signals limits the maximum frequency of the external clock signal
Solution Approach 1:
The patent applies preliminary action by reading data from the memory cell array and holding it in latches (L1, L2) before the external clock signal requires output. This advance preparation ensures data is ready in advance of the clock signal's rising or falling edges, enabling synchronous output without waiting for data preparation during critical clock transitions.
Solution Approach 2:
The patent segments the data path into multiple independent latches (L1, L2) that can be controlled independently. This segmentation allows different portions of data to be prepared at different times and output on different clock edges (rising or falling), effectively doubling the data throughput capacity and enabling higher external clock frequencies.
2Productivity
If the external clock signal frequency is increased for high-speed data output, then continuous read speed improves, but data destruction occurs at frequencies above 90 MHz due to timing conflicts
Solution Approach 1:
The patent employs dynamic control of the latches where each latch can be independently configured to output data on either the rising edge or falling edge of the external clock signal. This dynamic adaptability allows the system to adjust timing relationships in real-time, preventing data destruction by ensuring proper setup and hold times are met even at frequencies above 90 MHz.
Solution Approach 2:
The patent utilizes periodic action by outputting data on alternating clock edges (rising and falling edges) rather than requiring all data to be output on a single edge. This periodic distribution of data output across multiple clock cycles enables higher sustained throughput frequencies without compromising data integrity.
3Productivity
If multiple latches are used for independent data transmission and ECC processing, then high-speed continuous read is enabled, but the complexity of timing coordination between internal and external clocks increases
Solution Approach 1:
The patent implements self-service through automatic timing control circuits that autonomously manage the complex timing coordination between multiple latches and the external clock signal. The system automatically selects which latch outputs data on which clock edge without requiring external intervention, reducing the perceived complexity for users while maintaining high-speed performance.
Solution Approach 2:
The patent creates universal timing control that can accommodate multiple latches outputting data on different clock edges using a unified control mechanism. This multi-functional timing controller can dynamically assign different latches to different clock edges based on data readiness, simplifying the overall timing coordination while maximizing data throughput.
Data Source
AI summary
A semiconductor storage apparatus capable of realizing continuous read with high speed is provided. A continuous read method of a NAND flash memory includes: a step for holding setting information related to a read time of a memory cell array in continuous read in a register; a step for reading data from the memory cell array in the read time based on the setting information; a step for holding the read data in a latch (L1) and a latch (L2); and a step for outputting the data held synchronously with an external clock signal corresponding to the setting information.