NAND Flash Dual Trim Programming for Write Speed and Endurance
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Solution Overview
Problem
Non-volatile memory systems, such as NAND flash memory, face challenges in balancing high performance write speeds with memory endurance due to the stress of frequent programming and erase cycles, which limits their lifetime and reliability.
Innovation Solution
Implementing a dual performance trim mode where high performance trim is used for host writes and high endurance trim is used for background operations, with differing programming algorithms and step sizes, and weighting program/erase cycles differently to extend memory life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high performance programming algorithms are used to increase write speed, then productivity is improved, but memory cell stress increases causing reduced reliability and shorter lifetime
Solution Approach 1:
The patent applies dynamics by making the programming algorithm adaptive - it dynamically switches between high performance trim (HPT) and high endurance trim (HET) based on the operation type. HPT with larger step sizes is used for host writes to maximize speed, while HET with smaller step sizes is used for background operations to reduce stress. This dynamic adjustment resolves the contradiction by optimizing for speed when possible and for reliability when necessary.
Solution Approach 2:
The patent changes programming parameters (step size, voltage levels) based on the operation type. HPT uses larger programming step sizes for faster writes, while HET uses smaller step sizes to distribute stress more evenly across memory cells. By varying these parameters according to whether the operation is a host write or background operation, the system achieves both high productivity and high reliability.
2Productivity
If high performance programming is used for all operations, then productivity is maximized, but the harmful effects of stress on memory cells increase significantly
Solution Approach 1:
The patent applies local quality by treating different types of write operations differently. Host writes receive HPT optimization for speed, while background operations (wear leveling, garbage collection, hot/cold data migration) receive HET optimization for reduced stress. This localized approach ensures that stress-intensive background operations do not generate excessive harmful effects while maintaining high performance for user-visible operations.
Solution Approach 2:
The patent converts the potentially harmful effect of frequent background operations into a benefit by using HET to minimize their stress impact. Background operations are necessary for memory health but generate stress; by applying HET with smaller step sizes, the patent reduces this harmful effect while still achieving the necessary wear leveling and data management functions.
3Reliability
If smaller programming step sizes are used to reduce stress, then reliability is improved, but write performance decreases
Solution Approach 1:
The patent makes the step size dynamic rather than fixed. HPT uses larger step sizes for fast host writes when performance is prioritized, while HET uses smaller step sizes for background operations when reliability is prioritized. This dynamic selection of step size based on operation type resolves the contradiction by allowing large steps when they don't harm reliability and small steps when they protect reliability.
Solution Approach 2:
The patent changes the programming step size parameter based on the operation type. For host writes, HPT uses larger step sizes to achieve faster programming. For background operations, HET uses smaller step sizes to distribute stress and improve endurance. This parameter change strategy allows the system to achieve both fast writes and high reliability in different contexts.
Data Source
AI summary
A non-volatile memory operates in a high perform mode when writing host data by using a first programming algorithm. When performing background operations, the non-volatile memory writes data using a lower performance, but higher endurance programming algorithm. In both cases the data is written in the same multi-level format, but the higher endurance programming algorithm uses, for example, a staircase waveform with a smaller step size. A count is kept for the number of program/erase cycles for memory blocks for both types of programming trim, but where a high performance write is weighted more heavily than a high endurance write.