NAND Flash Soft-Bit Decoding With Dynamic LLR Table Selection
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Solution Overview
Problem
Existing memory systems face challenges in improving operation reliability and data transfer speed due to the broadening of threshold distributions in NAND flash memory cells, leading to reading errors and increased latency in error correction processes.
Innovation Solution
A memory system that includes a controller maintaining log likelihood ratio (LLR) tables, which are dynamically selected based on the number of write, erase, and read operations to optimize soft-decision decoding, thereby improving error correction efficiency and data transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single LLR table is used for error correction, then the device complexity is reduced, but the reliability deteriorates due to broadening threshold distributions under different operational conditions
Solution Approach 1:
The patent divides a single LLR table into multiple segment tables, where each segment table stores LLR values for a specific range of threshold voltage distributions. The controller segments the operational conditions and selects appropriate segment tables based on the current threshold distribution characteristics, thereby improving error correction accuracy without requiring a completely separate table for each condition.
Solution Approach 2:
The patent implements dynamic selection of LLR tables based on operational conditions such as the number of program/erase cycles. The controller dynamically determines which LLR table or segment table to use by monitoring P/E cycle counts and threshold distribution characteristics, allowing the system to adapt to changing memory cell conditions and maintain high reliability throughout the device lifecycle.
2Reliability
If multiple LLR tables are maintained for different operational conditions, then the reliability is improved, but the loss of time increases due to table selection overhead
Solution Approach 1:
The patent pre-calculates and stores multiple LLR tables and segment tables during manufacturing or initialization, each optimized for specific operational conditions. The controller pre-determines the appropriate table to use based on monitored parameters such as P/E cycle counts, eliminating the need for complex real-time calculations and reducing table selection time during actual error correction operations.
3Productivity
If traditional hard decision decoding is used, then the device complexity is low, but the productivity deteriorates due to increased error correction time under high P/E cycle conditions
Solution Approach 1:
The patent applies soft decision decoding with specific LLR tables or segment tables tailored to particular operational conditions (e.g., low P/E cycles vs. high P/E cycles) rather than uniformly applying soft decision decoding to all cases. This localized approach applies the more complex decoding method only where necessary, improving data transfer speed under high P/E cycle conditions while minimizing the overhead in other scenarios.
4Reliability
If the LLR table is not updated based on P/E cycle counts, then the ease of operation is maintained, but the reliability deteriorates due to threshold distribution broadening
Solution Approach 1:
The patent implements a feedback mechanism where the controller monitors the number of program/erase cycles and threshold distribution characteristics of the NAND flash memory, then uses this information to select or switch between appropriate LLR tables and segment tables. This feedback-driven approach automatically adapts the error correction process to current memory conditions, maintaining high reliability without requiring manual intervention.
Data Source
AI summary
A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.