Multi-Level NAND Flash ECC Allocation by Page Error Likelihood
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Solution Overview
Problem
In multi-level cell NAND flash memory devices, errors are not uniformly distributed across memory cells, leading to varying likelihoods of error occurrence, which existing error correction methods do not adequately address, resulting in inefficiencies in error correction resources allocation.
Innovation Solution
The solution involves dynamically allocating more error correction cells to the pages with higher error likelihood and reducing error correction cells for less error-prone pages, while also storing block management data only in the less error-prone pages to optimize error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform error correction is applied to all bits in multi-level cell memory, then implementation is simple, but error correction effectiveness is reduced due to non-uniform error distribution
Solution Approach 1:
The patent applies different error correction code strengths to different bit positions based on their error likelihood. Specifically, first page data bits are protected with a first ECC strength while second page data bits are protected with a second ECC strength, matching the local error characteristics of each bit position rather than applying uniform protection across all bits.
Solution Approach 2:
The patent segments the error correction protection into different levels corresponding to different page data bits. By dividing the error correction resources into multiple strength levels and assigning them to different bit groups, the system achieves differentiated protection without requiring completely separate error correction systems for each bit.
2Reliability
If more error correction resources are allocated to all bits, then error correction capability improves, but memory density and storage efficiency decrease
Solution Approach 1:
The patent allocates error correction resources according to the local error characteristics of different bit positions. Bits with higher error likelihood receive stronger ECC protection, while bits with lower error likelihood receive weaker protection, optimizing the overall error correction capability while minimizing the total number of ECC bits required.
Solution Approach 2:
The patent applies excessive error correction only where necessary - specifically to first page data bits that have higher error likelihood - rather than applying full-strength error correction uniformly to all bits. This partial application of strong error correction maintains reliability for critical bits while preserving memory density.
3Productivity
If error correction data is stored in dedicated areas for each page, then error correction efficiency improves, but memory area utilization decreases
Solution Approach 1:
The patent stores error correction data in dedicated spare areas associated with specific pages, allowing efficient error correction processing for each page independently. The first spare area stores ECC data for first page data bits, and the second spare area stores ECC data for second page data bits, enabling targeted and efficient error correction.
Solution Approach 2:
The patent extracts error correction data from the main data storage area and places it in dedicated spare areas. This separation allows the error correction data to be processed independently and efficiently while keeping the main data area optimized for data storage, improving overall system productivity.
Data Source
AI summary
Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.