NAND Flash ECC Buffering for Faster Sector Read Correction
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Solution Overview
Problem
In NAND-type flash memory, the narrow bit width of the SPI DO terminal leads to prolonged data transmission times, causing idle states in the controller chip and inefficiencies in pipeline processing, while increased memory array integration results in larger page buffer/sensing circuits, necessitating a reduction in chip area and cost.
Innovation Solution
The implementation of a semiconductor storage device with a NAND chip and a separate ECC chip, where the ECC chip alternately holds data of even- and odd-numbered sectors, allowing for faster error detection and correction, and utilizing a dedicated port for data transmission between the NAND and ECC chips to enhance processing speed and reduce chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted through the SPI DO terminal with narrow bit width, then data transmission is performed, but data transmission time is prolonged and pipeline processing efficiency is reduced
Solution Approach 1:
The patent segments the data transmission process by separating even-numbered and odd-numbered sectors into different holding portions (first holding portion and second holding portion). This allows parallel processing of different sector groups, effectively increasing data transmission speed and reducing overall transmission time while avoiding the bottleneck of narrow bit width SPI DO terminal
Solution Approach 2:
The patent implements preliminary action by pre-organizing sector data into even and odd groups in separate holding portions before transmission. This pre-segregation enables the ECC chip to process multiple sectors simultaneously through parallel decoding operations, significantly reducing the time required for error detection and correction while maintaining high data transmission speed
2Quantity of substance
If the memory array integration is increased, then storage capacity is improved, but the page buffer/sensing circuit area increases
Solution Approach 1:
The patent divides the sector data into two separate holding portions (first and second) based on even and odd sector numbers. This segmentation allows the ECC chip to process smaller data units in parallel, reducing the area requirement for the page buffer/sensing circuit while maintaining high storage capacity through efficient use of space
Solution Approach 2:
The patent introduces a new dimension of data organization by separating sectors into even and odd groups across different holding portions. This dimensional reorganization enables parallel processing paths, effectively increasing processing capacity without proportionally increasing chip area, thus improving storage efficiency
3Reliability
If the ECC chip processes all sectors sequentially, then error detection and correction is performed, but processing speed is reduced
Solution Approach 1:
The patent segments the ECC processing workload by dividing sectors into even-numbered and odd-numbered groups stored in separate holding portions. This segmentation enables the ECC chip to process multiple sectors simultaneously through parallel decoding operations, significantly improving processing speed while maintaining reliable error detection and correction for all sectors
Solution Approach 2:
The patent implements continuous useful action by maintaining both first and second holding portions actively populated with sector data ready for processing. This continuous availability of processed data in both holding portions allows the ECC chip to operate continuously without idle periods, maximizing processing speed while ensuring reliable error correction across all sectors
Data Source
AI summary
The disclosure provides a semiconductor storage device and a reading method that can achieve high-speed processing of error detection and correction and miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip includes a memory array, and a page buffer/sensing circuit including a latch (L1) and a latch (L2). The ECC chip includes RAM_E and RAM_O. The RAM_E and RAM_O hold the read data output from the latches (L1, L2) of the NAND chip. RAM_E holds the data of the even-numbered sectors, and RAM_O holds the data of the odd-numbered sectors. Making RAM_E or RAM_O alternately hold the data of the sectors can reduce the data size of RAM_E and RAM_O.