NAND Flash ECC Bypass for Specific Bit Strings
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Solution Overview
Problem
The increasing integration of semiconductor memories, such as NAND flash, leads to longer programming times due to the time-consuming ECC operations required for error checking and correction, especially as the number of bits per page increases, which obstructs the reduction of programming time while maintaining data reliability.
Innovation Solution
A semiconductor memory device and method that includes a detecting element to identify specific bit strings, allowing the transfer and ECC code writing to bypass the ECC operation, thereby reducing data transfer time and programming time by using a logic circuit to generate and write known ECC codes for specific bit strings directly, without performing ECC operations on them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC operation is performed on all programmed page data, then data reliability is improved, but programming time increases
Solution Approach 1:
The patent applies partial action by performing ECC operations only on data that requires error correction. A detection circuit identifies specific bit patterns (such as all-0 or all-1 patterns) that do not require ECC processing, allowing the system to skip ECC operations for these cases while maintaining reliability for data that actually needs protection.
Solution Approach 2:
The patent changes the parameter of ECC processing by introducing conditional logic based on data pattern detection. Instead of uniformly applying ECC to all data, the system dynamically adjusts processing based on the detected bit patterns, using different processing paths for different data types.
2Quantity of substance
If the number of bits per page increases due to higher integration, then memory capacity is improved, but ECC operation time increases
Solution Approach 1:
As page size increases with higher integration, the patent applies partial action by detecting specific bit patterns and skipping ECC operations for patterns that don't require correction. This reduces the effective processing load proportionally rather than linearly with page size.
Solution Approach 2:
The patent segments the ECC processing task by dividing pages into regions that require ECC processing and regions that don't, based on pattern detection. This allows parallel processing paths where detected patterns are handled differently from undetected patterns.
Data Source
AI summary
A semiconductor memory device is provided to keep data reliability while decreasing programming time. A NAND flash memory loads programming data from an external input/output terminal to a page buffer/sense circuit. A detecting circuit for monitoring the programming data detects whether the programming data is a specific bit string. If it is detected that the programming data is not a specific bit string, a transferring/writing circuit transfers the programming data kept by the page buffer/sense circuit to an error checking correction (ECC) circuit, and an ECC code generated by an ECC operation is written to the page buffer/sense circuit. If it is detected that the programming data is a specific bit string, transfer of the programming data kept by the page buffer/sense circuit is forbidden and a known ECC code corresponding to the specific bit string is written to the page buffer/sense circuit.