NAND Flash ECC Data Recovery via Cell Error Flipping
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Solution Overview
Problem
In NAND flash memory, when the total number of errors exceeds the error correction capability of ECC, the data becomes unrecoverable, leading to potential loss of important metadata and file system data, rendering SSDs unusable.
Innovation Solution
A controller is implemented to identify and salvage data from failed pages by flipping data values in cells with program/erase cycling errors, excluding transient errors, and performing error correction decoding to reduce the total number of errors below the ECC threshold, thereby recovering previously unrecoverable data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC is used to correct data errors, then data reliability is improved, but when errors exceed ECC capability, data loss occurs
Solution Approach 1:
The patent performs preliminary identification of bad blocks and bad pages before ECC decoding. By pre-locating cells that fail erase identification or have program errors, the system prepares error location information in advance, allowing ECC to focus correction efforts on remaining uncertainties and提高 correction efficiency
Solution Approach 2:
The patent changes the parameter of error correction by introducing bad block and bad page identification results as additional parameters to the ECC decoding process. This transforms the traditional ECC correction capability into an enhanced correction capability that leverages pre-identified error locations to recover data that would otherwise be unrecoverable
2Device complexity
If traditional ECC decoding is performed on data with excessive errors, then decoding complexity is reduced, but data recovery success rate decreases
Solution Approach 1:
The system performs preliminary scanning and identification of bad blocks and bad pages before ECC decoding. This preliminary action marks cells with erase failures or program errors, providing the ECC decoder with prior knowledge about certain error locations, thereby improving the probability of successful decoding without significantly increasing overall complexity
3Ease of operation
If all error types are treated uniformly by ECC, then processing simplicity is maintained, but correction effectiveness decreases for program/erase cycling errors
Solution Approach 1:
The patent applies different processing quality to different error types by identifying and marking bad blocks and bad pages separately. Cells that fail erase identification or have program errors are treated with special attention through marking, while other cells undergo standard ECC processing. This localized differentiation improves correction effectiveness for program/erase cycling errors while maintaining overall processing efficiency
Data Source
AI summary
An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page.