NAND Flash ECC Folding for Variable Page Lengths
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Solution Overview
Problem
Current NAND Flash systems face performance degradation due to variable page sizes, three-dimensional stacking, and higher program and erase cycles, which require stronger error correction schemes that decrease code rate and throughput.
Innovation Solution
Implementing bit-level granularity for NAND Flash page sizes and using a single error correction code throughout the lifespan, with techniques such as generating extended user data, parity data, and parity extension, and employing iterative soft-decision decoding processes to maintain performance without degrading the NAND Flash package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable page sizes are implemented to allow additional management information, then adaptability is improved, but device complexity increases due to varying ECC and CRC mechanisms
Solution Approach 1:
The patent implements a universal ECC mechanism that handles multiple page sizes (512B, 4KB, and variable sizes) through a single code structure. The LDPC encoder and decoder are designed to work with any page size by adjusting the codeword length parameter, eliminating the need for separate ECC mechanisms for different page sizes. This universal approach maintains adaptability while reducing device complexity.
2Quantity of substance
If three-dimensional stacking is used to increase package density, then capacity is improved, but reliability deteriorates due to increased noise and error rates
Solution Approach 1:
The patent employs iterative soft-decision decoding that dynamically adjusts decoding parameters based on the number of P/E cycles and observed error patterns. The decoder uses confidence values and threshold adjustments to adapt to increasing noise levels from 3D stacking and aging, maintaining reliable error correction despite deteriorating signal quality over time and across stacked chips.
3Reliability
If stronger error correction schemes are applied to handle increased noise from stacking and P/E cycles, then reliability is improved, but productivity decreases due to lower code rate
Solution Approach 1:
The patent implements dynamic code rate adjustment where the ECC strength is adapted based on the actual error conditions and P/E cycle count. The system starts with stronger error correction for highly degraded pages but can use weaker correction for cleaner data, optimizing the balance between reliability and throughput. The iterative decoding process also dynamically adjusts the number of iterations based on convergence criteria, avoiding unnecessary computational overhead.
4Adaptability or versatility
If multiple ECC and CRC mechanisms are used to support variable page sizes, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal ECC mechanism that handles multiple page sizes (512B, 4KB, and variable sizes) through a single code structure. The LDPC encoder and decoder are designed to work with any page size by adjusting the codeword length parameter, eliminating the need for separate ECC mechanisms for different page sizes. This universal approach maintains adaptability while reducing device complexity.
Data Source
AI summary
Disclosed are methods and devices for supporting multiple page lengths with unique error correction coding via Galois field dimension folding. In one embodiment, a method comprises receiving a write instruction, the write instruction including user data; generating extended user data based on the user data, the extended user data including at least one symbol comprising a bit of the user data and a pre-stored bit pattern; generating parity data by encoding the extended user data; generating parity extension data by encoding the bit of the user data; writing a codeword to a page of a non-volatile memory device, the codeword including the parity extension data, the user data, and the parity data.