NAND Flash ECC Layout for Word-Line Cut Retention Errors
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Solution Overview
Problem
As semiconductor memory devices, such as flash memory, are scaled down and memory cells are stacked, they experience degradation, leading to poor data retention and increased error rates.
Innovation Solution
A storage device with an error correction code (ECC) engine that groups memory cells into outer and inner cells based on their distance from word-line cut regions, performing first and second ECC encoding and decoding operations to enhance error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked and fabrication process is scaled-down, then storage capacity is increased, but data retention characteristics are degraded
Solution Approach 1:
The patent divides memory cells into outer cells (closer to word-line cut regions with higher error probability) and inner cells (farther from cut regions with lower error probability). Different ECC encoding operations are applied to each segment, with outer cells receiving more robust error correction treatment, thereby resolving the contradiction between increased storage capacity through stacking and maintaining data retention characteristics.
Solution Approach 2:
The patent applies different error correction strategies to different spatial locations within the memory array. Outer cells near word-line cut regions undergo first ECC encoding operations with higher correction capability, while inner cells undergo second ECC encoding operations. This localized differentiation maintains reliability in high-error zones while preserving overall storage capacity.
2Quantity of substance
If memory cells are stacked vertically, then storage density is improved, but error rates increase
Solution Approach 1:
The patent segments the vertically stacked memory cells into outer and inner groups based on their horizontal distance from word-line cut regions. This segmentation allows differential error correction treatment that addresses the increased error rates in stacked configurations without sacrificing storage density.
Solution Approach 2:
The patent changes the ECC encoding parameters based on cell location: outer cells use first ECC encoding operations with higher correction capability, while inner cells use second ECC encoding operations. This parameter differentiation resolves the contradiction between maintaining high storage density through vertical stacking and managing the concomitant increase in error rates.
3Reliability
If ECC encoding operations are performed on all memory cells uniformly, then error correction capability is maintained, but processing complexity increases
Solution Approach 1:
The patent segments the error correction process into two distinct operations: first ECC encoding for outer cells and second ECC encoding for inner cells. This segmentation maintains comprehensive error correction capability while optimizing processing complexity by applying appropriate correction levels to each segment rather than uniformly to all cells.
Solution Approach 2:
The patent applies partial error correction action differentiated by location: outer cells receive more extensive first ECC encoding treatment due to higher error probability, while inner cells receive less intensive second ECC encoding treatment. This partial differentiation maintains necessary error correction capability while reducing overall processing complexity compared to uniform treatment of all cells.
Data Source
AI summary
A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.