NAND Flash ECC Decoding With Cell-Specific LLR for Data Retention
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Solution Overview
Problem
As semiconductor memory devices, such as flash memory, are scaled down and memory cells are stacked, they experience degradation, leading to poor data retention and increased error rates.
Innovation Solution
A storage device with a nonvolatile memory device and a storage controller that groups target memory cells into outer and inner cells based on their location index, using different log likelihood ratio (LLR) values for error correction code (ECC) decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked and fabrication process is scaled-down, then storage capacity is improved, but data retention characteristic is degraded
Solution Approach 1:
The patent applies different LLR value strategies to different spatial locations within the memory block. Outer cells (closer to word-line cut regions) receive different LLR treatment compared to inner cells (farther from cut regions), acknowledging that error characteristics vary by location due to manufacturing variations and degradation patterns.
Solution Approach 2:
The patent dynamically adjusts LLR values based on read voltage levels and cell location. By changing the LLR parameter according to the read operation conditions and cell position, the system adapts to varying error rates caused by scaling and stacking effects, thereby improving overall data retention.
2Quantity of substance
If memory cells are stacked vertically, then storage density is improved, but error rate is increased
Solution Approach 1:
The patent recognizes that vertically stacked cells exhibit location-dependent error characteristics. Cells closer to word-line cut regions experience different error rates compared to cells farther away. By applying location-specific LLR values, the system compensates for these variations and reduces overall error rates in high-density stacked configurations.
Solution Approach 2:
The patent divides the memory block into distinct regions (outer cells and inner cells) with different error characteristics. This segmentation allows independent error correction strategies for each region, improving the effectiveness of ECC in vertically stacked high-density memory structures.
3Reliability
If different LLR values are applied to outer and inner cells, then error correction capability is improved, but processing complexity is increased
Solution Approach 1:
The patent implements a practical local quality approach by applying different LLR values only to cells adjacent to word-line cut regions versus other cells. This targeted differentiation improves error correction where most needed while avoiding excessive complexity across the entire memory array.
Solution Approach 2:
The patent applies enhanced error correction (different LLR values) selectively to specific cell regions rather than uniformly across all cells. This partial application of the more complex correction method achieves most of the error correction benefit while limiting the increase in processing complexity to only the necessary portions of the memory array.
Data Source
AI summary
A storage device, including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array including a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes, and a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells into outer cells and inner cells. The storage controller includes an error correction code (ECC) decoder configured to perform an ECC decoding operation by obtaining outer cell bits and inner cell bits during a read operation on the plurality of target memory cells, and applying different log likelihood ratio (LLR) values to the outer cell bits and the inner cell bits.