NAND Flash Memory Error Correction Output During Concurrent Multi-Plane Reading
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Solution Overview
Problem
NAND flash memories face challenges in efficiently performing error correction during concurrent operations like multi-plane and cache reading, where error correction results are not effectively outputted for each sector, leading to potential data corruption and increased load on the controller.
Innovation Solution
The semiconductor storage device incorporates an ECC circuit and a status register that concurrently execute error detection and correction processes, outputting error correction results for each sector during multi-plane, cache, and multi-plane cache reading operations, allowing the controller to determine refresh operations and ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed during concurrent operations (multi-plane/cache reading), then data integrity is maintained, but error correction results cannot be outputted for each sector
Solution Approach 1:
The patent divides the error correction results into per-sector units and maintains separate status registers for different planes and cache operations. This segmentation allows the system to track and output error correction results for each sector individually, resolving the contradiction between maintaining data integrity during concurrent operations and being able to output error correction results for each sector.
2Productivity
If concurrent operations are executed without per-sector error correction output, then operation speed is improved, but data corruption may occur
Solution Approach 1:
The patent implements feedback mechanisms through status registers that track error correction results for each sector during concurrent operations. The controller receives feedback about error correction status and can determine when refresh operations are needed, allowing the system to maintain both high operation speed and data integrity through informed decision-making during concurrent multi-plane and cache reading operations.
3Device complexity
If error correction results are not outputted for each sector, then device complexity is reduced, but controller load increases
Solution Approach 1:
The patent performs preliminary actions by pre-configuring status registers to track error correction results for each sector before concurrent operations begin. This preliminary setup allows the controller to efficiently manage and output error correction information without increasing operational complexity, as the tracking infrastructure is already in place and requires minimal additional processing during concurrent operations.
Data Source
AI summary
According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.