NAND Flash Page ECC Segmentation for Faster Read and Write
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Solution Overview
Problem
NAND type flash memory devices face challenges with weak error correction capabilities, leading to prolonged write and read times, necessitating large numbers of write/verify operations and redundant memory arrays, which increase cost and size.
Innovation Solution
Implementing a semiconductor memory device with a cell array that divides page data into sectors, adds check codes, and uses a latch circuit, data input/output portions, and a control circuit to manage and correct errors, enabling efficient error correction without redundant memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction capability is strengthened by using conventional ECC methods, then data reliability is improved, but write and read times are prolonged due to repeated verify operations
Solution Approach 1:
The patent divides page data into multiple sectors, with each sector having its own check code. This segmentation allows the error correction circuit to process and verify sectors independently rather than requiring repeated verify operations for the entire page, thereby reducing write and read times while maintaining error correction capability.
Solution Approach 2:
The patent adds check codes to each sector during the data input phase before writing to the memory array. This preliminary error detection preparation enables the error correction circuit to quickly identify and correct errors during read operations without requiring multiple verify cycles, thus reducing access time.
2Reliability
If conventional ECC methods are used to improve error correction, then data reliability is enhanced, but the system requires large numbers of write/verify operations and redundant memory arrays
Solution Approach 1:
The patent combines the error correction functionality directly into the data input/output circuits and control logic, merging these functions into the existing memory structure. This eliminates the need for separate redundant memory arrays while maintaining error correction capability, thereby reducing device complexity.
Solution Approach 2:
The error correction circuit uses check codes that are generated and stored within the same memory structure, allowing the system to perform error correction using its own internal resources rather than requiring external redundant memory. The error correction circuit processes sector data and check codes independently within the memory device.
3Reliability
If conventional ECC methods are implemented, then error correction is achieved, but memory size and production costs increase due to redundant memory requirements
Solution Approach 1:
By dividing page data into sectors with individual check codes, the patent reduces the overall redundancy ratio compared to conventional page-level ECC. Each sector requires a smaller check code (e.g., 4 bytes per sector) rather than a large check code for the entire page, thereby reducing total memory overhead and size.
4Productivity
If page data is written in units of pages to all memory cells connected to selected word lines, then write speed is improved, but variations in memory cell size cause distribution in write time requiring repeated verify operations
Solution Approach 1:
The patent divides page data into multiple sectors, allowing the write operation to progress through sectors independently. When a sector is successfully written and verified, processing can move to the next sector without waiting for other sectors, reducing the impact of write speed variations on overall write time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution strengthens error correction capabilities, reduces write and read times, eliminates the need for redundant memory, and decreases memory size and production costs, while maintaining high-speed data transfer and access.
Implementation Method 1
data is written into the memory transistors connected to the selected word lines all together in units of pages. Specifically, for example, a high voltage (for example, 18V) is applied to the selected word lines, 0V is applied to bit lines to which memory transistors into which data is to be written (0 data) are connected, and a high level voltage (for example, 3.3V) is applied to bit lines to which memory transistors for which the writing is to be prohibited (1 data) are connected. As a result, electrons are injected into the floating gates for only the selected memory transistors into which the data is to be written.
Data Source
AI summary
A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.