NAND Flash Memory Encoding for Inter-Cell Interference Reduction
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Solution Overview
Problem
Existing memory systems using NAND type flash memory face inefficiencies in writing data due to inter-cell interference and error correction challenges, particularly in multi-level cell configurations like TLC, which affect data reliability and storage efficiency.
Innovation Solution
A memory system that includes a memory controller and NAND-type flash memory, employing an error suppression encoding process using flags and randomization to optimize threshold voltage distributions, reducing cell deterioration and improving data reliability by converting user data into encoded forms that minimize error rates during writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction encoding is performed on all data before writing to NAND memory, then data reliability is improved, but writing efficiency deteriorates due to increased processing time
Solution Approach 1:
The patent applies error suppression encoding selectively only to specific data portions that require it, rather than performing full error correction encoding on all data. This partial action approach maintains data reliability for critical portions while avoiding the overhead of processing entire datasets, thus resolving the contradiction between reliability improvement and writing efficiency
Solution Approach 2:
The patent segments data into different portions and applies different encoding strategies to each segment. By dividing data into segments that require error suppression encoding and segments that don't, the system achieves reliable writing for critical data while maintaining overall writing efficiency, effectively resolving the contradiction between reliability and productivity
2Reliability
If randomization process is applied to data before encoding, then error suppression effectiveness is improved, but device complexity increases due to additional processing steps
Solution Approach 1:
The patent merges the randomization process with the error suppression encoding process into a unified operation. By combining these two functions into a single integrated process rather than executing them as separate steps, the system achieves effective error suppression while reducing the overall processing complexity and device requirements
Data Source
AI summary
A memory system includes a non-volatile memory including at least one memory cell, a buffer, and a memory controller. The memory controller acquires first data from the buffer. The first data includes a plurality of bits of data. The memory controller generates second data by performing a randomization process on the first data, generates a flag that is information used to identify an error suppression encoding process, based on the second data, and stores the flag in the buffer. The memory controller acquires third data and the flag from the buffer. The third data is 1-bit data of the first data. The memory controller generates storage data by performing the error suppression encoding process based on the acquired flag and the randomization process on the third data, and writes the storage data into the memory cell.