NAND Flash Memory Endurance via Lower Voltage Thresholds
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for storing compressed data in NAND flash memory require complex data mapping operations and utilize higher threshold voltage levels, which lead to increased wear on storage cells, reducing their lifespan.
Innovation Solution
The method employs lower threshold voltage levels, specifically E, P1, and P2, to represent compressed data states in multi-level cell NAND storage, reducing wear on storage cells by avoiding the use of higher voltage levels that cause greater wear.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher threshold voltage levels (P2, P3) are used to store compressed data, then storage capacity is improved, but wear on storage cells increases reducing lifespan
Solution Approach 1:
The patent changes the voltage threshold parameters used for data storage by utilizing lower voltage levels (E, P1) instead of higher voltage levels (P2, P3). This parameter change reduces the stress on storage cells during programming operations, thereby extending their lifespan while still maintaining adequate storage capacity through compressed data representation.
2Duration of action of stationary object
If data compression is implemented to extend NAND lifetime, then TBW is reduced improving endurance, but complex FTL and file system support is required
Solution Approach 1:
The patent changes the voltage threshold parameters used for data storage by utilizing lower voltage levels (E, P1) instead of higher voltage levels (P2, P3). This parameter change reduces the stress on storage cells during programming operations, thereby extending their lifespan while still maintaining adequate storage capacity through compressed data representation.
Data Source
AI summary
Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.