NAND Flash Cell Erase Control for Better Data Retention
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in performing erase operations on individual cells within a NAND string, leading to data failure and deterioration of cell characteristics, especially in three-dimensional structures, due to the lack of erase-protection conditions for other cells during erase operations, which can result in inaccurate data storage and reduced data retention.
Innovation Solution
A flash memory device and method that allows for selective erase operations on individual cells by controlling word lines, bit lines, and selection lines to generate gate-induced drain leakage (GIDL) specifically for the targeted cell, while preventing it from affecting unselected cells, using controlled voltage applications to adjust threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a block erase operation is performed to erase a specific flash memory cell, then the cell can be erased, but data failure occurs in cells with different threshold voltage characteristics and the number of operations increases
Solution Approach 1:
The patent segments the erase operation from the block level to the cell level by introducing a cell selection mechanism. The control circuit selectively activates only the specific flash memory cell for erase operation based on row and column selection signals, allowing individual cell erasure without affecting other cells in the block. This segmentation resolves the contradiction by enabling precise targeted erasure while preventing data failure in cells with different threshold voltage characteristics.
Solution Approach 2:
The patent applies local quality by creating a write-protection condition specific to unselected cells during erase operations. The control circuit sets a protection condition that prevents erase operations from affecting cells other than the selected target cell. This local protection mechanism ensures that only the intended cell undergoes erase operation, maintaining data integrity in other cells while achieving the goal of selective erasure.
2Reliability
If error correction technique is adopted to handle data failure, then data accuracy is maintained, but hardware and software resources are consumed
Solution Approach 1:
The patent implements preliminary action by establishing a write-protection condition before the erase operation begins. The control circuit pre-configures protection settings that prevent unintended erase operations on other cells during the erase process. This preliminary protective measure eliminates the need for subsequent error correction operations, reducing hardware and software resource consumption while maintaining data accuracy.
3Reliability
If multiple write and erase operations are performed on flash memory cells, then data can be corrected, but characteristics of the flash memory cells deteriorate
Solution Approach 1:
The patent extracts the erase operation from the block-level process and isolates it to the cell-level process. By using row and column selection signals to identify and protect specific cells, the system performs erase operations only on the necessary target cell rather than repeatedly processing entire blocks. This extraction approach minimizes the number of operations on individual cells, preserving cell characteristics while still enabling data correction through selective erasure and rewriting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention characteristics by precisely controlling erase operations, reducing power consumption, and minimizing the impact on unselected cells, thereby improving data stability and accuracy, particularly in neural network applications.
Implementation Method 1
an erase operation using gate induced drain leakage (GIDL)
Data Source
AI summary
A flash memory device includes a control circuit and a cell array including a first memory string including a plurality of first flash memory cells having control gates connected to a plurality of word lines, respectively, and a first bit line selection switch connecting the plurality of first flash memory cells to a first bit line in response to a voltage of a first drain selection line. The control circuit controls a first operation to program a selected flash memory cell with data so that a threshold voltage of the selected flash memory cell becomes greater than a first target threshold voltage and a second operation to erase the selected flash memory cell so that the threshold voltage becomes equal to or smaller than a target threshold voltage, the first target threshold voltage being greater than the target threshold voltage that is set according to the data.