NAND Flash Erase Page Detection Logic
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Solution Overview
Problem
Flash memory devices with NAND-based architecture face challenges in determining the availability of pages for writing due to inherent errors and disturbances, leading to time-intensive processing and reduced performance.
Innovation Solution
A method and system that reads a target page, identifies data errors as correctable or uncorrectable, sums the cumulative number of data bits with a value of zero, and compares it to a device threshold value to determine if the page is erased and available for writing, using error correction codes and a memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction approaches are used to detect and correct data errors in flash memory, then data reliability is improved, but processing time increases and performance is constrained
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the expected number of zero bits for each page in the flash memory device. When a page needs to be read, the system simply compares the actual zero bit count with the pre-stored expected value, rather than performing full error correction checking. This preliminary preparation eliminates time-consuming error analysis during actual read operations while maintaining data reliability through the pre-computed reference values.
Solution Approach 2:
The patent extracts only the essential information needed for error detection - the count of zero bits - from the full page data. Instead of analyzing entire pages or performing comprehensive error correction algorithms, the system isolates and compares just the zero bit count metric. This extraction approach significantly reduces processing time while still providing reliable error detection capability.
2Measurement precision
If comprehensive error checking and bad block management are implemented to ensure data accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the critical zero bit count metric from complex error analysis. By focusing solely on counting and comparing zero bits rather than implementing full error correction codes or comprehensive bad block management, the system achieves effective error detection with minimal control logic complexity. The pre-stored expected values provide a simple reference for comparison without requiring sophisticated algorithms.
Solution Approach 2:
The patent changes the approach from analyzing complex error patterns to using a single parameter - the count of zero bits. By transforming the error detection problem into a simple parameter comparison (actual zero count vs. expected zero count), the system maintains measurement precision while dramatically reducing device complexity. This parameter transformation eliminates the need for complex error correction logic.
3Reliability
If strict error correction approaches are used to ensure data accuracy, then reliability is improved, but productivity decreases due to additional processing overhead
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the expected zero bit counts during device initialization or manufacturing. This preliminary preparation allows subsequent read and verify operations to proceed without time-consuming error analysis, as the system simply compares actual counts against pre-stored references. This maintains data accuracy while eliminating processing overhead during operational cycles.
Solution Approach 2:
The patent applies partial action by performing only the minimal necessary check - comparing zero bit counts - rather than executing full error correction procedures. This partial checking approach provides sufficient reliability for flash memory operations while minimizing processing overhead and maximizing write/erase cycle speed. The system does exactly what is needed (zero count comparison) without unnecessary additional processing.
Data Source
AI summary
The present invention provides a method and system to reduce the impact of errors introduced in flash devices while providing improved system performance through optimized activities with limited impact to overhead using a predetermined threshold value or threshold device value. In an embodiment, a device threshold value is compared with the cumulative number of data bits having a zero value of a target page and an error type of the target page is assessed to determine whether the target page is available to be written to. Therefore for a highly effective method for is provided for determining the availability of a page, having a block address and page address, to be identified, in one instance, as being an erased page that is available to be written to.