NAND Flash Erase Flow for Neighbor Block Disturb Reduction
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Solution Overview
Problem
Erase disturb in neighboring memory blocks due to incomplete discharge of channel hole potential during erase operations in NAND flash memory, leading to soft erase of adjacent blocks.
Innovation Solution
Perform additional read operations on neighboring blocks after erasing a target block to discharge channel hole potentials, using specific voltage combinations to turn on and off select gate transistors, thereby reducing erase disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operation is performed on target block, then threshold voltage of memory cells in target block is changed, but channel hole potential is not fully discharged leading to soft erase of neighboring blocks
Solution Approach 1:
The patent applies preliminary action by performing read operations on neighboring blocks before completing the erase operation on the target block. Specifically, after erasing the target block, the method reads neighboring blocks to discharge their channel hole potentials before the erase operation is fully completed, preventing soft erase of adjacent blocks while maintaining erase reliability
Solution Approach 2:
The patent uses read operations as an intermediary mechanism to discharge channel hole potentials in neighboring blocks. The read operation acts as a mediator that transfers charge from the neighboring blocks' channels to the select gate, thereby eliminating the harmful channel hole potential without directly interfering with the target block's erase operation
2Object-affected harmful factors
If additional read operations are performed on neighboring blocks, then channel hole potentials are discharged reducing erase disturb, but operation time increases
Solution Approach 1:
The patent merges the read operation for discharge purposes with the normal read operation functionality. By combining these operations and using the same read circuitry and pathways, the patent eliminates the need for separate dedicated discharge operations, thereby reducing the additional time penalty while still achieving channel hole potential discharge
Solution Approach 2:
The patent maintains continuity of useful action by performing the discharge read operations during the erase operation timeframe rather than as separate sequential operations. The read operations are integrated into the erase operation flow, ensuring that the discharge action continues without interruption and completes within the existing operation window
Data Source
AI summary
Example memory devices, systems, and methods for reducing erase disturb in memory devices are disclosed. One example method includes erasing, during an erase operation of a block in a memory cell array, one or more memory cells in the block. It is verified, during the erase operation of the block, whether the one or more memory cells are erased. Each of one or more blocks in the memory cell array is respectively read during the erase operation of the block, where respectively reading each of the one or more blocks includes applying a first voltage to a first select gate line coupled to a first select gate transistor in the block, and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, where the first voltage is lower than the second voltage.