NAND Flash Memory Erase Disturb Reduction via Local Voltage Biasing
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Solution Overview
Problem
NAND flash memory devices experience erase disturb issues due to parasitic capacitance coupling, which affects neighboring cells during programming operations, leading to program disturb and potential loss of programmed threshold voltage.
Innovation Solution
Applying an initial negative voltage to specific word lines coupled to memory cells that share channels with the programmed cell, followed by a positive Vpass voltage, to reduce erase disturb effects by segmenting the memory block and isolating channels, thereby minimizing voltage swings and protecting already programmed cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an initial negative voltage is applied to unselected word lines to reduce program disturb, then program disturb is reduced, but erase disturb increases causing threshold voltage loss in programmed cells
Solution Approach 1:
The patent applies different voltage biases to different word lines based on their location relative to the selected word line. Specifically, unselected word lines adjacent to the selected word line receive a first bias voltage (e.g., 0V), while unselected word lines further away receive a second bias voltage (e.g., negative voltage). This local differentiation allows reduction of program disturb in adjacent cells while minimizing erase disturb in cells with lower threshold voltages, thus resolving the contradiction between reducing program disturb and preventing erase disturb.
2Reliability
If all unselected word lines are biased with negative voltage to protect from program disturb, then program disturb is reduced, but threshold voltage of programmed cells is reduced below programmed level
Solution Approach 1:
The patent implements location-based biasing where unselected word lines are assigned different bias voltages depending on their proximity to the selected word line. Word lines immediately adjacent to the selected word line are biased at a first voltage (e.g., 0V) to protect cells with low threshold voltages from erase disturb, while word lines further away are biased at a negative voltage to reduce program disturb. This localized quality control maintains precise threshold voltage control while still providing program disturb protection where needed.
Solution Approach 2:
The patent changes the bias voltage parameter of unselected word lines based on their location. By adjusting the voltage parameter differently for different groups of unselected word lines (those adjacent to selected vs. those farther away), the patent optimizes both program disturb reduction and threshold voltage maintenance, resolving the contradiction between these two requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces erase disturb by controlling voltage biases during programming, ensuring that only necessary cells are affected, thus maintaining the programmed state and preventing unintended changes in threshold voltage.
Implementation Method 1
parasitic capacitance coupling between the selected word line and adjacent word lines becomes problematic
Data Source
AI summary
A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.