NAND Flash Erase Pulse Control for Longer Block Lifespan
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Solution Overview
Problem
Non-volatile memory devices, such as NAND Flash memory, face limitations in the number of program/erase cycles, leading to premature failure of memory blocks due to excessive erasure, which current technologies fail to effectively manage.
Innovation Solution
An erase scheme is introduced that applies a first set of erase pulses with varying voltage values followed by a second set of pulses with a fixed, lower voltage when a cycle threshold is reached, terminating the process if a maximum cycle count is not met, thereby managing the number of erasures to prevent block failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high number of erase cycles is performed to ensure complete erasure, then erasure reliability is improved, but memory block lifespan deteriorates due to excessive erasures
Solution Approach 1:
The patent changes the voltage parameter of erase pulses dynamically based on the erase cycle count. During initial erase cycles, high voltage pulses are applied to ensure complete erasure. When the erase cycle count reaches a threshold, the voltage parameter is reduced to a lower level for subsequent cycles, thereby maintaining erasure reliability while reducing stress on the memory block to extend its lifespan.
2Manufacturing precision
If erase voltage is continuously applied at high level to ensure complete erasure, then erasure completeness is improved, but memory cell stress increases leading to premature failure
Solution Approach 1:
The patent implements periodic verification during the erase operation. After applying a certain number of erase pulses, a verification read is performed to check if erasure is complete. Based on the verification result, the erase operation is either terminated or continues with adjusted voltage levels, avoiding unnecessary continuous high-voltage application that would increase memory cell stress.
Solution Approach 2:
The voltage parameter of erase pulses is dynamically adjusted based on the erase cycle count and verification results. Initially, high voltage pulses ensure complete erasure. When the cycle count reaches a threshold or verification confirms complete erasure, the voltage is reduced or operation terminated, thereby ensuring erasure completeness while protecting memory cell reliability.
3Ease of operation
If erase operations are performed without cycle counting, then operational simplicity is maintained, but memory block failure occurs due to unmanaged erasure cycles
Solution Approach 1:
The patent implements automatic erase cycle counting and management within the memory device itself. The control logic automatically tracks the number of erase cycles, compares it against a predetermined threshold, and adjusts the erase operation accordingly without requiring external intervention. This self-service approach maintains operational simplicity while ensuring memory block reliability through proper cycle management.
Data Source
AI summary
In certain aspects, a memory device includes at least a block of memory cells and a peripheral circuit coupled to the block of memory cells. The peripheral circuit is configured to apply a first set of erase pulses to erase the block of memory cells in a first set of erase cycles, respectively. The first set of erase pulses includes one or more first erase voltages having varied voltage values. Responsive to an erase cycle count reaching a cycle threshold, the peripheral circuit is further configured to apply a second set of erase pulses to erase the block of memory cells in a second set of erase cycles, respectively. The second set of erase pulses includes one or more second erase voltages each of which has a respective voltage value smaller than a voltage value of one of the one or more first erase voltages.