NAND Flash Memory Cell Erase Voltage Segmentation
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Solution Overview
Problem
Current NAND flash memory erase operations result in varying erase threshold voltage distributions across memory cells due to processing variability, leading to unpredictable programming and data state distributions.
Innovation Solution
Applying different voltages to access lines during the erase pulse to de-bias and narrow the erase threshold voltage distribution, reducing the number of required voltage supplies and improving the predictability of data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single erase voltage is applied to all access lines during erase operation, then the erase operation is simple to implement, but the erase threshold voltage distribution varies widely across memory cells
Solution Approach 1:
The patent divides the access lines into multiple groups, where each group is assigned a specific bias voltage during the erase operation. This segmentation allows different portions of the memory array to receive tailored voltage conditions, thereby narrowing the overall erase threshold voltage distribution while maintaining manageable complexity through systematic grouping.
Solution Approach 2:
The patent applies different bias voltages to different groups of access lines based on their specific characteristics and positions within the memory array. This local quality approach ensures that each region receives the appropriate voltage conditions to achieve uniform erase thresholds, rather than applying a uniform voltage across the entire array.
2Reliability
If different voltages are applied to access lines during erase pulse to narrow the distribution, then the predictability of programming and data states improves, but the number of required voltage supplies increases
Solution Approach 1:
The patent segments access lines into groups that receive different bias voltages, enabling controlled variation in erase conditions across the array. This segmentation improves the predictability of programming and data states by ensuring more uniform erase thresholds, while the grouping strategy keeps the number of voltage supplies manageable.
Solution Approach 2:
The patent changes the bias voltage parameter applied to different groups of access lines during the erase operation. By systematically varying this parameter across groups rather than individually for each access line, the patent achieves improved data state predictability while limiting the increase in voltage supply complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach narrows the erase threshold voltage distribution, enhancing the predictability of programming and data states, while reducing the complexity and cost associated with multiple voltage sources.
Implementation Method 1
Applying different voltages to access lines during the erase pulse to de-bias and narrow the erase threshold voltage distribution
Data Source
AI summary
Memories having a controller configured to apply a first voltage level to channel regions of memory cells of an array of memory cells coupled to a plurality of access lines; apply a second voltage level, lower than the first voltage level, to a first access line; apply a third voltage level, lower than the second voltage level, to a second access line while applying the second voltage level to the first access line and while applying the first voltage level to the channel regions of the memory cells; and increase the voltage level applied to the second access line to the second voltage level and decrease the voltage level applied to the first access line to a fourth voltage level, lower than the second voltage level and different than the third voltage level, while applying the first voltage level to the channel regions of the memory cells.