NAND Flash Erase-State Tracking for Soft-Decision LLR Calculation
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Solution Overview
Problem
Conventional NAND flash memory devices do not provide soft decisions, making it difficult for SSD controllers to track erase states and calculate log likelihood ratios (LLRs) reliably, especially since the mean of the erase state voltage distribution can be below zero volts, which is not readable in normal operation mode.
Innovation Solution
A method and apparatus for tracking erase state voltage distributions in NAND flash memory using a look-up table that selects parameters based on channel statistics such as program/erase cycle count, retention time, and read disturb count, allowing for soft decoded error correction without firmware and enabling reliable read reference voltage and LLR calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash devices are used without soft decisions, then device complexity is reduced, but reliability of error correction deteriorates
Solution Approach 1:
The patent pre-calculates and stores voltage distribution parameters (mean, standard deviation) for different program/erase cycle counts in lookup tables before actual operation. This preliminary characterization eliminates the need for complex real-time calculations, enabling soft decision error correction with reduced controller complexity while maintaining high reliability
Solution Approach 2:
The patent introduces lookup tables as an intermediary between the flash memory and the error correction decoder. These tables store pre-computed voltage distribution parameters that mediate the conversion from raw flash reads to soft decision LLR values, simplifying the controller architecture while enabling reliable error correction
2Measurement precision
If erase state tracking is performed using conventional methods, then measurement precision of voltage distribution is improved, but ease of operation deteriorates due to inaccessible negative voltages
Solution Approach 1:
The patent shifts the measurement approach from directly reading inaccessible negative voltage regions to inferring erase state characteristics from accessible positive voltage readings. By tracking voltage distributions in the readable range and using statistical models to characterize the full distribution including the negative region, the system achieves precise erase state tracking without requiring direct access to negative voltages
Solution Approach 2:
The patent replaces direct electrical measurement of the erase state voltage distribution with a statistical modeling approach. Instead of physically accessing the negative voltage region through read operations, the system uses mathematical models and lookup tables to characterize the distribution based on program/erase cycle counts and accessible readings, eliminating the operational difficulty of negative voltage access
3Reliability
If repeated estimation of cell voltage distributions is performed, then reliability of channel tracking is improved, but loss of time increases due to frequent calibration operations
Solution Approach 1:
The patent performs voltage distribution characterization in advance and stores the results in lookup tables indexed by program/erase cycle count. During normal operation, the system simply queries the appropriate pre-computed parameters from the table based on the current P/E cycle count, eliminating the need for repeated time-consuming estimation operations while maintaining accurate channel tracking
Solution Approach 2:
The patent changes the approach from dynamically re-estimating voltage distributions to using pre-characterized parameters that vary with program/erase cycle count. By organizing lookup tables with P/E cycle count as the index and storing pre-computed mean and standard deviation values for each cycle count level, the system achieves fast parameter retrieval without repeated measurement operations
Data Source
AI summary
An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.