NAND Flash Erase Verify Using Constant Voltage Differences
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Solution Overview
Problem
Current techniques for verifying negative threshold voltages in non-volatile storage devices, such as NAND flash memory, are time-consuming and inefficient, particularly during erase and soft programming operations, due to the need for charging bit lines and applying negative voltages to word lines.
Innovation Solution
The method involves applying one or more erase pulses to non-volatile storage elements associated with bit lines and word lines, followed by sensing conditions on the bit lines with non-negative compare voltages while maintaining constant voltage differences, allowing for efficient verification of threshold voltages without applying negative voltages to the word lines, using a sense capacitor to speed up the charging process and reduce sensing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If negative voltages are applied to word lines for verifying negative threshold voltages, then verification accuracy is improved, but operation time increases and device complexity increases
Solution Approach 1:
Instead of applying negative voltages to verify negative threshold voltages, the patent inverts the approach by applying positive voltages to bit lines and sensing the resulting current flow. This allows verification of negative threshold voltages without requiring negative voltage generation, thereby reducing operation time and device complexity while maintaining verification accuracy
Solution Approach 2:
The patent introduces current sensing as an intermediary mechanism. Rather than directly measuring voltage conditions with negative voltages applied, the system uses current flow through the memory cell as a mediator to indirectly verify the threshold voltage state, eliminating the need for negative voltage generation circuitry
2Measurement precision
If bit lines are charged for sensing operations, then measurement precision is improved, but charging time increases
Solution Approach 1:
The patent performs preliminary charging of bit lines to a positive voltage level before the sensing operation begins. This pre-charging ensures that when the sensing phase starts, the bit lines are already at the required voltage level, eliminating the need for time-consuming charging during the actual sensing operation and thereby improving overall speed while maintaining sensing accuracy
Solution Approach 2:
The sensing operation is structured as a periodic process with distinct phases: a charging phase where bit lines are rapidly charged to positive voltage, followed by a sensing phase where current flow is measured. This periodic structure allows the system to optimize each phase independently, achieving both fast charging and accurate sensing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster and more efficient verification of negative threshold voltages, reducing the time required for erase and soft programming operations while minimizing power consumption and avoiding the challenges of generating negative voltages.
Implementation Method 1
An erase pulse moves the threshold voltage of the memory cells towards (or beyond) an erase target level, which may be below 0 Volts
Implementation Method 2
sensing conditions on the bit lines with non-negative compare voltages while maintaining constant voltage differences
Data Source
AI summary
Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.