NAND Flash Memory Cell Erase Voltage Modulation
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Solution Overview
Problem
Existing flash memory technologies face issues with over-erasing and stress on the tunnel oxide layer due to uniform erase voltage application, which does not account for physical variability and charge levels of individual cells, leading to data corruption and reduced endurance in multi-level cell NAND flash devices.
Innovation Solution
The erase voltage is modulated on a per-cell basis using bypass circuitry that adjusts the voltage based on the programming charge level of each floating gate, ensuring each cell is subjected only to the necessary voltage to restore its nominal 'erased' state, thereby reducing stress and preventing over-erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a uniform erase voltage is applied to all cells in a block, then the erase operation is simple and fast, but it causes over-erasing of cells with low charge levels and deep depletion of the floating gate
Solution Approach 1:
The patent applies different erase voltage levels to different cells based on their individual charge states. Cells are divided into groups (first group with higher charge, second group with lower charge), and each group receives a customized erase voltage. This local differentiation prevents over-erasing of already-low-charge cells while ensuring adequate erasure of high-charge cells, resolving the contradiction between uniform fast erasure and precise charge level control.
2Reliability
If a high erase voltage is applied to ensure complete erasure of all cells, then erasure reliability is improved, but stress on the tunnel oxide layer increases and cell endurance decreases
Solution Approach 1:
The patent dynamically adjusts the erase voltage parameter based on the charge level of each cell group. Instead of using a fixed high voltage for all cells, the system modifies the voltage parameter to match the actual needs of each group. This parameter adaptation ensures complete erasure where necessary while minimizing unnecessary high-voltage stress on the tunnel oxide layer, thereby preserving cell endurance.
3Reliability
If individual cell charge levels are monitored and tailored erase voltages are applied, then over-erasing is prevented and cell longevity is improved, but device complexity and control circuitry requirements increase
Solution Approach 1:
The patent segments the cell population into distinct groups based on their charge levels, with each group receiving customized erase treatment. This segmentation approach balances precision and complexity by grouping cells with similar characteristics together, allowing for simplified control logic that monitors and adjusts voltages at the group level rather than requiring individual cell-level control, thus managing device complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents deep depletion and over-erasing of cells, enhancing endurance and reducing unnecessary energy consumption by applying tailored erase pulses to each cell, ensuring accurate data storage and retrieval in NAND flash memory devices.
Implementation Method 1
The process of programming (writing 0's to) a NAND cell requires applying a programming charge to the floating gate by applying a programming voltage to the control gate, which causes the injection of electrons into the floating gate by quantum mechanical tunneling.
Implementation Method 2
The process of erasing (writing 1's to) a NAND cell requires removing the programming charge from the floating gate by applying an erase voltage to the device substrate, which pulls electrons from the floating gate.
Implementation Method 3
Erasing of the memory cells is accomplished by applying, for example, a 20V erase voltage to a page by closing the bitline select and the ground select transistors, thereby forcing the 20V erase voltage on the bitline to pass through the control gates, which exerts a Fowler-Nordheim field to deplete the floating gate of any program charge.
Data Source
AI summary
A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.