NAND Flash Erasing Method Suppressing Oxide Film Deterioration
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Solution Overview
Problem
In NAND-type flash memory, repeated programming and erasing operations lead to deterioration of the oxide film, causing conductance loss and reduced data retention, limiting the number of reliable data rewriting cycles.
Innovation Solution
An erasing method that applies an erasing voltage to the channel region of selected memory cells and immediately follows with a weak programming voltage to all control gates, suppressing charge trapping and oxide film deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If repeated programming and erasing operations are performed, then data rewriting capability is achieved, but oxide film deterioration occurs causing conductance loss and reduced data retention
Solution Approach 1:
The patent applies a preliminary high voltage to the control gate before the erasing operation to prevent hole injection into the oxide film. This preventive action is taken in advance of the erasing process that would otherwise cause oxide film deterioration, thereby maintaining reliability while enabling repeated data rewriting cycles
2Productivity
If high voltage is applied to P-well for erasing, then erasing operation is completed, but voltage fluctuation affects other nodes and causes reliability issues
Solution Approach 1:
The patent sets the control gate voltage to match the P-well voltage during the erasing operation, creating an equipotential condition. This prevents voltage fluctuation and potential difference that would otherwise cause harmful electric fields and reliability issues, while still allowing the erasing operation to proceed efficiently
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases the number of reliable data rewriting cycles by reducing oxide film deterioration, ensuring guaranteed reliability and improved data retention.
Implementation Method 1
applying an erasing voltage to the channel region of the selected memory cell, and erasing data of the charge storage layer of the selected memory cell
Implementation Method 2
immediately applying a weak programming voltage lower than a programming voltage in a programming time to all of the control gates of the selected memory cell after the erasing step, thereby uniformly performing week programming to the selected memory cell
Data Source
AI summary
An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).


