3D NAND Flash Memory Erasing Verification Control
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Solution Overview
Problem
In 3D NAND Flash memory devices, false error verification occurs due to rapid channel discharging, leading to over-erasure and degradation of reliability and programming performance.
Innovation Solution
The memory device maintains the bottom select gate on during a maintaining period before the top select gate is turned on during the verification stage, increasing channel discharging time to prevent voltage drops and false error verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the top select gate is turned on immediately after erasing, then the verification stage can start quickly, but the channel discharges too rapidly causing false error verification
Solution Approach 1:
The bottom select gate is turned on in advance during a maintaining period before the top select gate is turned on. This preliminary action prepares the channel discharge path, ensuring that when verification begins, the channel can discharge properly without rapid voltage drops, thus preventing false error verification while maintaining verification speed.
Solution Approach 2:
The patent dynamically controls the timing of select gate activation by introducing a maintaining period where the bottom select gate is turned on before the top select gate. This dynamic timing adjustment optimizes the channel discharge characteristics during verification, balancing speed and accuracy.
2Productivity
If the bottom select gate is turned off immediately after erasing, then the erasing operation completes faster, but voltage drops occur during verification causing false errors
Solution Approach 1:
The bottom select gate is kept on during a maintaining period that extends into the verification stage. This preliminary preparation ensures the channel remains conductive and ready for proper discharge during verification, preventing voltage drops and false errors while maintaining efficient erasing operation.
3Loss of time
If the channel discharges rapidly during verification, then the verification process is faster, but false error verification occurs
Solution Approach 1:
The patent implements dynamic control of the bottom select gate timing, maintaining it in the on state during a maintaining period before and during the early phase of verification. This dynamic adjustment optimizes channel discharge characteristics, achieving reliable verification without excessive time loss.
Data Source
AI summary
A memory device includes a memory string and a control circuit. The memory string includes a top select gate, a memory cell, and a bottom select gate. The top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line. The control circuit is coupled to the first select line, the word line, and the second select line. The control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage, apply an erasing voltage to the memory string in the erasing stage, apply a first voltage to the word line in a first stage of the verification stage, apply a second voltage lower than the first voltage to the word line in a second stage after the first stage, apply a first turn-on voltage to the second select line before applying the second voltage to the word line, and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.