NAND Flash Error Estimation for Asymmetric ECC Decoding
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Solution Overview
Problem
In data storage devices like NAND flash memory, the asymmetric error ratio between bits being read as a one when they are truly zero and bits being read as zero when they are truly one is not known until decoding, which hinders decoding performance, especially as the device approaches its end of life due to electrical and physical failures.
Innovation Solution
Estimating the asymmetric error ratio before the ECC decoding procedure using voltage measurements and hard decoding, and using this ratio as input for the decoding process to improve bit error rate performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard ECC decoding is performed without prior error ratio estimation, then the decoding process is simple and fast, but the bit error rate performance deteriorates as the device approaches end of life due to asymmetric errors
Solution Approach 1:
The patent performs preliminary error ratio estimation before the main ECC decoding process. A hard decoding is executed first to estimate asymmetric error ratios (E01 and E10), which then inform the subsequent soft decoding process. This preliminary action allows the decoder to adapt to the actual error characteristics of the memory device, improving reliability without completely redesigning the decoding architecture.
Solution Approach 2:
The patent implements a feedback mechanism where the results of hard decoding (error ratios E01 and E10) are fed back into the soft decoding process. The estimated error ratios are used to adjust the decoding parameters and improve the accuracy of error correction. This feedback loop enables the system to adapt to changing error patterns as the device ages.
2Reliability
If voltage measurements and hard decoding are performed to estimate error ratios, then decoding performance improves, but the read operation time and processing overhead increase
Solution Approach 1:
The patent applies partial hard decoding to estimate error ratios rather than performing complete accurate decoding. The hard decoding provides sufficient information (error ratios E01 and E10) for the soft decoding to function effectively, without requiring the full precision that would be needed for perfect error correction. This partial action reduces processing time while maintaining improved performance over standard decoding.
Solution Approach 2:
The error ratio estimation is performed as a preliminary step that reuses voltage measurements already taken for the read operation. Rather than adding completely separate measurement processes, the patent utilizes the existing read voltage data to perform hard decoding and extract error ratios, minimizing additional time overhead.
3Reliability
If asymmetric error ratios are not accounted for, then the decoding process remains simple, but error correction capability is insufficient for aged memory devices
Solution Approach 1:
The patent applies different decoding strategies to different error types based on their asymmetric characteristics. The soft decoding process uses the estimated error ratios (E01 for 0→1 errors and E10 for 1→0 errors) to apply locally optimized correction rules. This local quality approach allows the decoder to handle asymmetric errors more effectively without completely overhauling the entire decoding procedure.
Solution Approach 2:
The patent changes the parameters used in the decoding process by incorporating error ratio estimates (E01 and E10) into the soft decoding algorithm. These parameter changes allow the decoder to adapt its behavior based on the actual error characteristics observed in the memory device, improving error correction capability for aged devices without requiring a fundamentally different decoding architecture.
Data Source
AI summary
Techniques related to improving a performance related to at least data reads from a memory are described. In an example, data is stored in a block of the memory as codewords. A data read includes a determination of whether each bit from a portion of the block is a zero or a one based on voltage measurements. Prior to decoding the codewords by performing a decoding procedure by an ECC decoder of the memory, a first number of errors “E01” and a second number of errors “E10” are estimated, where the first number of errors “E01” is associated with bits each being a true zero and erroneously determined as a one, and where the second number of errors “E10” associated with bits each being a true one and erroneously determined as a zero. Thereafter, the decoding of the codewords based on the decoding procedure is performed.