NAND Flash Block Usability Detection via Failure Counting
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Solution Overview
Problem
Conventional flash memory devices face issues with reducing the number of bad blocks, which affects the yield rate and utilization efficiency of memory arrays due to incomplete erasing verification and programming failures.
Innovation Solution
Implementing a method to detect and manage failures among NAND strings in semiconductor storage devices by applying an erasing pulse and determining the usability of blocks based on the number of failures, with error correction capabilities to ensure accurate programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional erasing verification is performed by reverse reading to reduce power consumption, then power consumption is reduced, but the number of bad blocks increases due to incomplete detection of erasing failures
Solution Approach 1:
The verification process is segmented into two distinct phases: reverse reading verification for power efficiency and normal reading verification for accuracy. The controller selectively applies each verification method based on the detection results, with normal reading used to confirm the absence of bad blocks after initial reverse reading passes. This segmentation allows the system to benefit from both low-power operation and reliable bad block detection.
Solution Approach 2:
Reverse reading verification is performed as a preliminary screening step before normal reading verification. This preliminary action filters out obviously good blocks using low-power reverse reading, while reserving normal reading for cases where bad blocks might be present. The preliminary reverse reading reduces the overall number of high-power normal reading operations needed, thereby reducing total power consumption while maintaining detection accuracy.
2Measurement precision
If the number of verification steps is increased to improve detection accuracy, then detection accuracy is improved, but processing time increases
Solution Approach 1:
The verification process dynamically adjusts the number of verification steps based on the detection results of previous steps. If reverse reading verification passes, the system may skip or reduce normal reading verification steps, adapting the verification intensity to the actual block quality. This dynamic approach ensures high detection accuracy for problematic blocks while minimizing processing time for good blocks.
Solution Approach 2:
The controller uses feedback from reverse reading verification results to determine the extent of subsequent normal reading verification needed. When reverse reading indicates potential issues, the system intensifies normal reading verification; when reverse reading confirms good blocks, the system reduces verification intensity. This feedback mechanism optimizes the balance between detection accuracy and processing time by avoiding unnecessary verification steps on already-verified blocks.
Data Source
AI summary
A semiconductor memory device, an erasing method and a programming method are provided. The semiconductor memory device includes a memory array, which includes a plurality of NAND strings; a page buffer/sensing circuit, which is connected to the NAND strings of the memory array through bit lines and outputs whether the NAND strings include failures; and a detecting circuit, which is connected to the plurality of page buffer/sensing circuits and detects a number of the failures among the NAND strings of a selected block. The block is determined to be usable when the number of the failures among the NAND strings detected by the detecting circuit is less than or equal to a fixed number, and the block is determined to be unusable as a bad block when the number of the failures exceeds the fixed number.