NAND Flash Memory Flag Cell Array Alternating Write Pattern

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Solution Overview

Problem

Conventional NAND-type flash memories experience reliability issues with flag data due to capacitive coupling, leading to fluctuations in threshold values and poor data reliability.

Innovation Solution

The memory cell array is structured such that flag cells are written with data alternately in both the bit line and word line directions, reducing the influence of capacitive coupling and maintaining data reliability by minimizing threshold value fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If flag cells are written with data continuously in conventional NAND flash memory, then data storage capacity is utilized, but capacitive coupling causes threshold value fluctuations and reduces data reliability

Engineering Contradiction:

Improveflag data reliabilityVSAvoidcapacitive coupling influence

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the flag cell area into multiple sections and writes data to alternating memory cells in a segmented pattern. Instead of writing to all flag cells continuously, the invention segments the writing process by selecting every other memory cell (e.g., cells at even or odd positions) to reduce capacitive coupling between adjacent written cells, thereby maintaining data reliability while utilizing storage capacity.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If more memory cells are written with data to increase storage utilization, then capacity is improved, but threshold value fluctuations increase due to capacitive coupling

Engineering Contradiction:

Improvedata storage capacityVSAvoidthreshold value stability

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating different writing patterns in different regions of the flag cell area. By alternating which memory cells receive data writes (e.g., writing to even-positioned cells in one operation and odd-positioned cells in another), the invention ensures that local capacitive coupling effects are minimized in each region, thereby maintaining threshold value stability across the entire array while maximizing overall storage utilization.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the impact of capacitive coupling on flag cells, ensuring reliable data storage by stabilizing threshold values and maintaining the integrity of flag data.

Implementation Method 1

The reliability of a conventional NAND-type flash memory's flag data has been damaged due to the influence of capacitive coupling

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS7505318B2Nonvolatile semiconductor memory device

Publication Date: 2009.03.17 KIOXIA CORP

AI summary

A nonvolatile semiconductor memory device of the present invention is characterized in that, when data is written to a flag cell area, every other flag cell in the direction of one bit line BL among a plurality of flag cells 15 connected to the bit line BL is written with data and every other flag cell in the direction of one word line WL among a plurality of flag cells 15 connected to the word line WL is written with data. The arrangement as described above prevents a flag cell 15 from being influenced by the capacitive coupling of a neighboring flag cell 15 adjacent to the flag cell 15 in the direction of the word line WL. Thus, data (flag data) memorized by the flag cell 15 can have improved reliability.