NAND Flash Memory Floating Gate Segmentation for Reliability
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Solution Overview
Problem
NAND flash memory faces challenges in data read/write reliability due to limitations in existing designs, particularly in the number of data storage units and the complexity of charge management across floating gates, leading to reduced read/write cycle efficiency and shorter usage lifetime.
Innovation Solution
The design incorporates multiple floating gates, inter-gate dielectric layers, and control gates surrounded by dielectric layers to enhance data storage units, allowing for improved charge management and reliability through precise electric field control, increasing the read/write cycle index and usage lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple floating gates are added to each data storage unit, then data read/write reliability is improved, but device complexity increases
Solution Approach 1:
The data storage unit is segmented into multiple floating gates (first floating gate and second floating gate) with separate control gates (first control gate and second control gate). This segmentation allows independent charge management for each floating gate, enabling more reliable data storage and retrieval while maintaining organized structural complexity through functional division.
2Reliability
If inter-gate dielectric layers are added between floating gates, then charge management is improved, but manufacturing complexity increases
Solution Approach 1:
Inter-gate dielectric layers are introduced as intermediary materials between adjacent floating gates and control gates. These dielectric layers act as mediators that prevent charge leakage and interference between neighboring gates, improving charge management reliability. The standardized dielectric layer integration follows conventional semiconductor manufacturing processes, balancing manufacturing feasibility with enhanced charge isolation.
3Reliability
If dielectric layers surround and connect floating gates and control gates, then capacitive coupling consistency is improved, but loss of energy increases
Solution Approach 1:
Dielectric layers are strategically positioned to surround and connect floating gates and control gates at specific locations where capacitive coupling is needed. This localized approach ensures consistent capacitive coupling characteristics where required while minimizing dielectric material usage elsewhere, thereby reducing overall energy loss through the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data read/write reliability by maintaining consistent capacitive coupling and reducing leakage, thereby extending the usage lifetime and improving the overall performance of NAND flash memory.
Implementation Method 1
maintaining consistent capacitive coupling
Implementation Method 2
at least two inter-gate dielectric layers respectively formed on the two floating gates
Implementation Method 3
allowing for improved charge management and reliability through precise electric field control
Data Source
AI summary
A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.