NAND Flash Gate Doping Sequence for Wider Etch Window
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Solution Overview
Problem
The existing NAND flash manufacturing methods face challenges in maintaining the gate etching process window while ensuring product device performance, as high phosphorus doping reduces the critical dimension of the polysilicon control gate, leading to reduced coupling capacitance and impaired erasing and writing speeds.
Innovation Solution
A method involving a lower initial doping concentration for the polysilicon control gate, followed by self-aligned ion implantation to increase the doping to the target concentration, ensuring the polysilicon control gate width and overlap area are sufficient, thereby enhancing coupling capacitance and maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high phosphorus doping concentration is used for the polysilicon control gate, then the coupling capacitance between control gate and floating gate is improved, but the critical dimension of the polysilicon control gate is reduced
Solution Approach 1:
The patent divides the doping process into two separate stages: first forming the polysilicon control gate with a lower initial doping concentration to maintain critical dimension, then performing subsequent ion implantation to increase the doping concentration. This segmentation allows independent optimization of each parameter without compromising the other.
Solution Approach 2:
The patent performs the preliminary action of forming the polysilicon control gate with controlled lower doping before the final doping enhancement. This preliminary structure ensures the critical dimension is established and maintained, preventing collapse before the doping concentration is increased through ion implantation.
2Speed
If high phosphorus doping concentration is used for the polysilicon control gate, then the erasing and writing speeds are improved, but the gate etching process window is reduced
Solution Approach 1:
The patent segments the process into gate formation with controlled doping followed by separate ion implantation, allowing the gate etching process to be performed with optimal lower doping concentration that maintains a wide process window, while achieving high performance speeds through subsequent doping enhancement.
Solution Approach 2:
The preliminary gate formation is performed with lower doping concentration that provides a wide etching process window, ensuring robust manufacturing. The high-speed performance is then achieved through preliminary structure validation followed by ion implantation doping enhancement.
3Device complexity
If the polysilicon control gate width is reduced through high doping, then the manufacturing complexity is reduced, but the overlap area with floating gate is reduced
Solution Approach 1:
The patent segments the structure formation and doping enhancement into separate steps, allowing the polysilicon control gate to maintain its full width and overlap area during formation, while achieving simplified manufacturing characteristics through controlled lower doping concentration that prevents structural complexity issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the gate etching process window and device performance by reducing polysilicon control gate width reduction, ensuring the polysilicon control gate does not collapse and maintaining strong coupling with the floating gate, thus improving erasing and writing speeds.
Implementation Method 1
the formation process of the polysilicon control gate adopts an in-situ doping solution, i.e., doping with phosphorus and carbon elements
Implementation Method 2
self-aligned ion implantation to increase the doping to the target concentration
Data Source
AI summary
The present application discloses a method for manufacturing a NAND flash, comprising: step 1, sequentially form a floating gate dielectric layer and a first polysilicon layer; step 2, sequentially forming an inter-gate dielectric layer and a second polysilicon layer, wherein a first doping concentration of the second polysilicon layer is less than a target doping concentration; step 3, forming a pattern transfer mask layer; step 4, patterning the pattern transfer mask layer; step 5, performing gate etching, wherein the first and second polysilicon layers subjected to the gate etching respectively form a polysilicon floating gate and the polysilicon control gate; step 6, forming a first spacer, wherein the first spacer in a storage area fully fills a first interval area; and step 7, performing self-aligned ion implantation to increase a doping concentration of the polysilicon control gate to the target doping concentration.