NAND Flash Gate Isolation Spacer Prevents Silicide Protrusions
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Solution Overview
Problem
Current NAND flash memory devices experience poor electrical performance due to the formation of protruded sharp portions in the metal silicide layer at the bottom corner of the unit groove, which lowers the breakdown voltage.
Innovation Solution
An isolation spacer layer is formed on the side wall of the unit groove to prevent the metal silicide layer from forming on the side wall of the first gate laminated structure at the bottom corner, thereby avoiding the formation of protruded sharp portions and increasing the breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal layer is conformally formed covering the first gate laminated structure and unit dielectric layer, then the metal silicide layer can be formed through annealing, but protruded sharp portions are formed at the bottom corner of the unit groove which lowers the breakdown voltage
Solution Approach 1:
An isolation spacer layer is introduced as an intermediary between the metal layer and the first gate laminated structure at the bottom corner of the unit groove. This spacer layer prevents direct contact and subsequent silicide formation between the metal layer and the gate structure, eliminating the formation of protruded sharp portions and improving breakdown voltage.
Solution Approach 2:
The isolation spacer layer is selectively formed only at the bottom corner of the unit groove where the metal layer contacts the unit dielectric layer, rather than uniformly across the entire structure. This localized approach prevents silicide formation only where it would create harmful protrusions, while allowing metal silicide formation elsewhere to maintain low resistance.
2Reliability
If the isolation spacer layer is formed on the side wall of the unit groove, then the metal silicide layer is prevented from forming on the side wall of the first gate laminated structure at the bottom corner, but the device complexity increases
Solution Approach 1:
The isolation spacer layer is formed only at the specific bottom corner region of the unit groove where it is needed to prevent harmful silicide formation, rather than adding spacers throughout the entire device. This localized modification minimizes the increase in device complexity while achieving the reliability improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the electrical performance of the semiconductor structure by preventing the formation of protruded sharp portions in the metal silicide layer, thereby enhancing the breakdown voltage and overall performance of the NAND flash memory device.
Implementation Method 1
annealing the metal layer to form a metal silicide layer
Implementation Method 2
the metal layer is configured to form a metal silicide layer
Data Source
AI summary
A semiconductor structure and a method for forming same are provided. In one form a method includes: providing a substrate with a discrete first gate laminated structure formed on the substrate; forming, on a portion of the substrate exposed from the first gate laminated structure, a unit dielectric layer covering a portion of a side wall of the first gate laminated structure, where the first gate laminated structure and the unit dielectric layer enclose a unit groove; forming an isolation spacer layer on a side wall of the unit groove, where the isolation spacer layer is in contact with the unit dielectric layer; forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and annealing the metal layer to form a metal silicide layer. In implementations of the present disclosure, the metal layer is isolated from the first gate laminated structure at a bottom corner of the unit groove using the isolation spacer layer, to prevent a metal silicide layer from being formed at the bottom corner of the unit groove, so that the metal silicide layer is unlikely to have a protruded sharp portion, thereby increasing a breakdown voltage of a unit memory area. Therefore, electrical performance of the semiconductor structure is optimized.