NAND Flash Cell Selective Erase Through GIDL Voltage Control
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Solution Overview
Problem
Conventional NAND flash memory devices lack the ability to perform an erase operation on a single flash memory cell within a NAND string, requiring block-level operations, which can lead to data failure and increased wear due to mismatched threshold voltage characteristics, especially in three-dimensional structures, and necessitate resource-intensive error correction techniques.
Innovation Solution
A flash memory device and method that controls voltage differences between bit lines and string selection lines to induce gate-induced drain leakage (GIDL) for selective erase operations on individual cells, while maintaining voltage disparities between selected and unselected cells to prevent unintended erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If block-level erase operation is performed, then erase operation can be executed, but data failure may occur due to threshold voltage mismatch and increased wear
Solution Approach 1:
The patent divides the block-level erase operation into cell-level erase operations by introducing selective erase capability. The control circuit enables individual cell erasure within a NAND string by controlling string selection lines and bit lines, allowing only the target cell to be erased while preserving others. This segmentation resolves the contradiction by providing fine-grained erase control that prevents data failure from threshold voltage mismatch.
Solution Approach 2:
The patent applies local quality by creating different voltage conditions for selected and unselected cells. The control circuit sets specific voltage levels on string selection lines and bit lines so that only the selected cell experiences the voltage conditions necessary for erase operation, while unselected cells remain unaffected. This localized approach maintains data accuracy by preventing unintended erasure.
2Ease of operation
If block-level erase operation is performed, then erase operation can be executed, but number of write and erase operations increases leading to characteristic deterioration
Solution Approach 1:
The patent segments the erase operation to affect only the specific cell needing erasure rather than the entire block. By controlling string selection lines and bit lines selectively, the system performs cell-level erasure, significantly reducing the frequency of operations on any single cell and thereby extending flash memory cell lifespan.
Solution Approach 2:
The patent extracts the erase operation from the block level down to the cell level. The control circuit enables the system to target and erase only the specific problematic cell, separating the erase operation from the broader block operation. This extraction minimizes unnecessary operations on other cells, reducing cumulative wear and extending the overall memory device lifespan.
3Ease of operation
If conventional erase operation is used, then erase can be performed, but hardware and software resources are consumed for error correction
Solution Approach 1:
The patent extracts the need for error correction by preventing data failures in the first place. By enabling cell-level erase operations, the system can correct threshold voltage mismatches without requiring block-level erases and subsequent error correction codes. This extraction eliminates the need for complex ECC hardware and software, reducing device complexity.
Solution Approach 2:
The patent performs preliminary cell-level erase operations to prevent data failures before they occur. By selectively erasing cells with threshold voltage mismatches, the system proactively maintains data integrity, eliminating the need for subsequent error correction operations and reducing hardware/software resource requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise erasure of single flash memory cells, reducing power consumption and hardware/software resource demands, and maintains data accuracy by minimizing unintended erasure, particularly beneficial for neural networks and multi-level data storage.
Implementation Method 1
the control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced leakage (GIDL) at the first bit line selection switch
Data Source
AI summary
A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.