NAND Flash Memory Cell Array GIDL Mitigation via Threshold Segmentation
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Solution Overview
Problem
Existing NAND-type non-volatile semiconductor memory devices suffer from miswriting due to gate-induced-drain leakage (GIDL), which occurs when high electrical fields concentrate, leading to current leakage and hot carrier generation, especially when writing data and applying inverted bias voltage.
Innovation Solution
The solution involves a non-volatile semiconductor memory device with a memory cell array where each memory cell transistor is set to different threshold voltages, connected in series between selection transistors on two terminals of a bit line, and a control circuit that records two values for first memory cell transistors and more than three values for second transistors, using programming/verifying voltages lower than the maximum threshold voltage to prevent miswriting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dummy transistors are inserted into the bit line to maintain memory capacity, then memory capacity is preserved, but gate-induced-drain leakage (GIDL) increases causing miswriting
Solution Approach 1:
The invention extracts the harmful function of dummy transistors (which cause GIDL) while preserving their beneficial role in maintaining memory capacity. This is achieved by replacing dummy transistors with actual memory cell transistors that are configured not to store data but to maintain the electrical characteristics of the bit line without generating leakage current.
Solution Approach 2:
The invention applies local quality by differentiating the function of specific transistors within the memory cell array. Transistors adjacent to selection transistors are configured with specific threshold voltage characteristics that prevent GIDL while maintaining capacity. This localized functional differentiation allows the system to preserve memory capacity in specific regions without incurring the harmful GIDL effect throughout the entire bit line.
2Reliability
If high voltage is applied to control gate for write-in operation, then electrons are injected into floating gate for data storage, but hot carriers are generated causing miswriting in adjacent cells
Solution Approach 1:
The invention segments the memory cell structure into distinct functional regions with different threshold voltage characteristics. By setting specific threshold voltages for transistors adjacent to selection transistors, the patent creates electrical isolation that prevents hot carriers generated during write-in operations from affecting adjacent memory cells, while still allowing proper electron injection into the floating gate for data storage.
Solution Approach 2:
The invention changes the threshold voltage parameter of specific memory cell transistors to prevent hot carrier injection. By adjusting the threshold voltage of transistors adjacent to selection transistors to be higher than the bit line selection control voltage, the patent modifies the electrical characteristics to block hot carrier flow while maintaining the ability to perform reliable data storage in other cells.
3Ease of operation
If bit line selection control voltage is set high for programming, then selected memory cell can be programmed, but breakdown occurs at diffusion layer edge causing hot electron injection
Solution Approach 1:
The invention changes the threshold voltage parameter of specific transistors to create a voltage barrier that prevents breakdown at the diffusion layer edge. By setting the threshold voltage of transistors adjacent to selection transistors higher than the bit line selection control voltage, the patent modifies the electrical characteristics to eliminate the breakdown condition while preserving the programming capability of selected memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate-induced-drain leakage (GIDL) and miswriting, while maintaining memory capacity by using single-level cells adjacent to selection transistors and multi-level cells, thereby ensuring reliable data recording.
Implementation Method 1
electrons are injected from the semiconductor substrate into the floating gate, thereby making the threshold voltage higher than the write-in threshold voltage
Implementation Method 2
a high voltage, such as 20V, is applied to a semiconductor substrate thereof and 0V is applied to a word line thereof. As such, electrons are pulled out from a floating gate
Implementation Method 3
gate-induced-drain leakage (GIDL) may be generated on the two adjacent bit lines WL0 and WL31, so as to result in miswriting... current leakage increases and hot carriers are generated due to high electrical field effect
Data Source
AI summary
A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in series between selection transistors Qs1 and Qs2 on two terminals of a selected bit line; and a control circuit 11 for controlling writing of the data from the memory cell array 10. The control circuit 11 records two values for at least a plurality of first memory cell transistors Q0, Q1, Q32 and Q33 respectively adjacent to the selection transistors Qs1 and Qs2 on two terminals of the bit line, and records more than three values for a plurality of second transistors Q2˜Q31 other than the first memory cell transistors.